1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #ifndef _ICE_COMMON_H_ 5 #define _ICE_COMMON_H_ 6 7 #include <linux/bitfield.h> 8 9 #include "ice.h" 10 #include "ice_type.h" 11 #include "ice_nvm.h" 12 #include "ice_flex_pipe.h" 13 #include "ice_parser.h" 14 #include <linux/avf/virtchnl.h> 15 #include "ice_switch.h" 16 #include "ice_fdir.h" 17 18 #define ICE_SQ_SEND_DELAY_TIME_MS 10 19 #define ICE_SQ_SEND_MAX_EXECUTE 3 20 21 #define FEC_REG_SHIFT 2 22 #define FEC_RECV_ID_SHIFT 4 23 #define FEC_CORR_LOW_REG_PORT0 (0x02 << FEC_REG_SHIFT) 24 #define FEC_CORR_HIGH_REG_PORT0 (0x03 << FEC_REG_SHIFT) 25 #define FEC_UNCORR_LOW_REG_PORT0 (0x04 << FEC_REG_SHIFT) 26 #define FEC_UNCORR_HIGH_REG_PORT0 (0x05 << FEC_REG_SHIFT) 27 #define FEC_CORR_LOW_REG_PORT1 (0x42 << FEC_REG_SHIFT) 28 #define FEC_CORR_HIGH_REG_PORT1 (0x43 << FEC_REG_SHIFT) 29 #define FEC_UNCORR_LOW_REG_PORT1 (0x44 << FEC_REG_SHIFT) 30 #define FEC_UNCORR_HIGH_REG_PORT1 (0x45 << FEC_REG_SHIFT) 31 #define FEC_CORR_LOW_REG_PORT2 (0x4A << FEC_REG_SHIFT) 32 #define FEC_CORR_HIGH_REG_PORT2 (0x4B << FEC_REG_SHIFT) 33 #define FEC_UNCORR_LOW_REG_PORT2 (0x4C << FEC_REG_SHIFT) 34 #define FEC_UNCORR_HIGH_REG_PORT2 (0x4D << FEC_REG_SHIFT) 35 #define FEC_CORR_LOW_REG_PORT3 (0x52 << FEC_REG_SHIFT) 36 #define FEC_CORR_HIGH_REG_PORT3 (0x53 << FEC_REG_SHIFT) 37 #define FEC_UNCORR_LOW_REG_PORT3 (0x54 << FEC_REG_SHIFT) 38 #define FEC_UNCORR_HIGH_REG_PORT3 (0x55 << FEC_REG_SHIFT) 39 #define FEC_RECEIVER_ID_PCS0 (0x33 << FEC_RECV_ID_SHIFT) 40 #define FEC_RECEIVER_ID_PCS1 (0x34 << FEC_RECV_ID_SHIFT) 41 42 int ice_init_hw(struct ice_hw *hw); 43 void ice_deinit_hw(struct ice_hw *hw); 44 int ice_check_reset(struct ice_hw *hw); 45 int ice_reset(struct ice_hw *hw, enum ice_reset_req req); 46 int ice_create_all_ctrlq(struct ice_hw *hw); 47 int ice_init_all_ctrlq(struct ice_hw *hw); 48 void ice_shutdown_all_ctrlq(struct ice_hw *hw, bool unloading); 49 void ice_destroy_all_ctrlq(struct ice_hw *hw); 50 int 51 ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq, 52 struct ice_rq_event_info *e, u16 *pending); 53 int 54 ice_get_link_status(struct ice_port_info *pi, bool *link_up); 55 int ice_update_link_info(struct ice_port_info *pi); 56 int 57 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 58 enum ice_aq_res_access_type access, u32 timeout); 59 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res); 60 int 61 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res); 62 int 63 ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res); 64 int ice_aq_alloc_free_res(struct ice_hw *hw, 65 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 66 enum ice_adminq_opc opc); 67 bool ice_is_sbq_supported(struct ice_hw *hw); 68 struct ice_ctl_q_info *ice_get_sbq(struct ice_hw *hw); 69 int 70 ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq, 71 struct ice_aq_desc *desc, void *buf, u16 buf_size, 72 struct ice_sq_cd *cd); 73 void ice_clear_pxe_mode(struct ice_hw *hw); 74 int ice_get_caps(struct ice_hw *hw); 75 76 void ice_set_safe_mode_caps(struct ice_hw *hw); 77 78 int ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 79 u32 rxq_index); 80 81 int 82 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params); 83 int 84 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params); 85 int 86 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 87 struct ice_aqc_get_set_rss_keys *keys); 88 int 89 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 90 struct ice_aqc_get_set_rss_keys *keys); 91 92 bool ice_check_sq_alive(struct ice_hw *hw, struct ice_ctl_q_info *cq); 93 int ice_aq_q_shutdown(struct ice_hw *hw, bool unloading); 94 void ice_fill_dflt_direct_cmd_desc(struct ice_aq_desc *desc, u16 opcode); 95 extern const struct ice_ctx_ele ice_tlan_ctx_info[]; 96 int ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx, 97 const struct ice_ctx_ele *ce_info); 98 99 extern struct mutex ice_global_cfg_lock_sw; 100 101 int 102 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, 103 void *buf, u16 buf_size, struct ice_sq_cd *cd); 104 int ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd); 105 106 int 107 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 108 struct ice_sq_cd *cd); 109 int 110 ice_aq_set_port_params(struct ice_port_info *pi, bool double_vlan, 111 struct ice_sq_cd *cd); 112 int 113 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 114 struct ice_aqc_get_phy_caps_data *caps, 115 struct ice_sq_cd *cd); 116 bool ice_is_pf_c827(struct ice_hw *hw); 117 bool ice_is_phy_rclk_in_netlist(struct ice_hw *hw); 118 bool ice_is_clock_mux_in_netlist(struct ice_hw *hw); 119 bool ice_is_cgu_in_netlist(struct ice_hw *hw); 120 bool ice_is_gps_in_netlist(struct ice_hw *hw); 121 int 122 ice_aq_get_netlist_node(struct ice_hw *hw, struct ice_aqc_get_link_topo *cmd, 123 u8 *node_part_number, u16 *node_handle); 124 int 125 ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 126 enum ice_adminq_opc opc, struct ice_sq_cd *cd); 127 int 128 ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps); 129 void 130 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 131 u16 link_speeds_bitmap); 132 int 133 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 134 struct ice_sq_cd *cd); 135 bool ice_is_generic_mac(struct ice_hw *hw); 136 bool ice_is_e810(struct ice_hw *hw); 137 int ice_clear_pf_cfg(struct ice_hw *hw); 138 int 139 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 140 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd); 141 bool ice_fw_supports_link_override(struct ice_hw *hw); 142 int 143 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 144 struct ice_port_info *pi); 145 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps); 146 int ice_aq_get_phy_equalization(struct ice_hw *hw, u16 data_in, u16 op_code, 147 u8 serdes_num, int *output); 148 int 149 ice_aq_get_fec_stats(struct ice_hw *hw, u16 pcs_quad, u16 pcs_port, 150 enum ice_fec_stats_types fec_type, u32 *output); 151 152 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps); 153 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options); 154 int 155 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, 156 bool ena_auto_link_update); 157 int 158 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 159 enum ice_fc_mode req_mode); 160 bool 161 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *caps, 162 struct ice_aqc_set_phy_cfg_data *cfg); 163 void 164 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, 165 struct ice_aqc_get_phy_caps_data *caps, 166 struct ice_aqc_set_phy_cfg_data *cfg); 167 int 168 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 169 enum ice_fec_mode fec); 170 int 171 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 172 struct ice_sq_cd *cd); 173 int 174 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd); 175 int 176 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 177 struct ice_link_status *link, struct ice_sq_cd *cd); 178 int 179 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 180 struct ice_sq_cd *cd); 181 int 182 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd); 183 184 int 185 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 186 struct ice_sq_cd *cd); 187 int 188 ice_aq_get_port_options(struct ice_hw *hw, 189 struct ice_aqc_get_port_options_elem *options, 190 u8 *option_count, u8 lport, bool lport_valid, 191 u8 *active_option_idx, bool *active_option_valid, 192 u8 *pending_option_idx, bool *pending_option_valid); 193 int 194 ice_aq_set_port_option(struct ice_hw *hw, u8 lport, u8 lport_valid, 195 u8 new_option); 196 int 197 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 198 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 199 bool write, struct ice_sq_cd *cd); 200 u32 ice_get_link_speed(u16 index); 201 202 int 203 ice_cfg_vsi_rdma(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 204 u16 *max_rdmaqs); 205 int 206 ice_ena_vsi_rdma_qset(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 207 u16 *rdma_qset, u16 num_qsets, u32 *qset_teid); 208 int 209 ice_dis_vsi_rdma_qset(struct ice_port_info *pi, u16 count, u32 *qset_teid, 210 u16 *q_id); 211 int 212 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 213 u16 *q_handle, u16 *q_ids, u32 *q_teids, 214 enum ice_disq_rst_src rst_src, u16 vmvf_num, 215 struct ice_sq_cd *cd); 216 int 217 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 218 u16 *max_lanqs); 219 int 220 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 221 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 222 struct ice_sq_cd *cd); 223 int 224 ice_aq_cfg_lan_txq(struct ice_hw *hw, struct ice_aqc_cfg_txqs_buf *buf, 225 u16 buf_size, u16 num_qs, u8 oldport, u8 newport, 226 struct ice_sq_cd *cd); 227 int ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle); 228 void ice_replay_post(struct ice_hw *hw); 229 struct ice_q_ctx * 230 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle); 231 int ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in, u16 flag); 232 int 233 ice_aq_get_cgu_abilities(struct ice_hw *hw, 234 struct ice_aqc_get_cgu_abilities *abilities); 235 int 236 ice_aq_set_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 flags1, u8 flags2, 237 u32 freq, s32 phase_delay); 238 int 239 ice_aq_get_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 *status, u8 *type, 240 u8 *flags1, u8 *flags2, u32 *freq, s32 *phase_delay); 241 int 242 ice_aq_set_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 flags, 243 u8 src_sel, u32 freq, s32 phase_delay); 244 int 245 ice_aq_get_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 *flags, 246 u8 *src_sel, u32 *freq, u32 *src_freq); 247 int 248 ice_aq_get_cgu_dpll_status(struct ice_hw *hw, u8 dpll_num, u8 *ref_state, 249 u8 *dpll_state, u8 *config, s64 *phase_offset, 250 u8 *eec_mode); 251 int 252 ice_aq_set_cgu_dpll_config(struct ice_hw *hw, u8 dpll_num, u8 ref_state, 253 u8 config, u8 eec_mode); 254 int 255 ice_aq_set_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx, 256 u8 ref_priority); 257 int 258 ice_aq_get_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx, 259 u8 *ref_prio); 260 int 261 ice_aq_get_cgu_info(struct ice_hw *hw, u32 *cgu_id, u32 *cgu_cfg_ver, 262 u32 *cgu_fw_ver); 263 264 int 265 ice_aq_set_phy_rec_clk_out(struct ice_hw *hw, u8 phy_output, bool enable, 266 u32 *freq); 267 int 268 ice_aq_get_phy_rec_clk_out(struct ice_hw *hw, u8 *phy_output, u8 *port_num, 269 u8 *flags, u16 *node_handle); 270 int ice_aq_get_sensor_reading(struct ice_hw *hw, 271 struct ice_aqc_get_sensor_reading_resp *data); 272 void 273 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 274 u64 *prev_stat, u64 *cur_stat); 275 void 276 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 277 u64 *prev_stat, u64 *cur_stat); 278 bool ice_is_e810t(struct ice_hw *hw); 279 bool ice_is_e822(struct ice_hw *hw); 280 bool ice_is_e823(struct ice_hw *hw); 281 bool ice_is_e825c(struct ice_hw *hw); 282 int 283 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 284 struct ice_aqc_txsched_elem_data *buf); 285 int 286 ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value, 287 struct ice_sq_cd *cd); 288 int 289 ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, 290 bool *value, struct ice_sq_cd *cd); 291 bool ice_is_100m_speed_supported(struct ice_hw *hw); 292 u16 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high); 293 int 294 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size, 295 struct ice_sq_cd *cd); 296 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw); 297 int 298 ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add); 299 int ice_lldp_execute_pending_mib(struct ice_hw *hw); 300 int 301 ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 302 u16 bus_addr, __le16 addr, u8 params, u8 *data, 303 struct ice_sq_cd *cd); 304 int 305 ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 306 u16 bus_addr, __le16 addr, u8 params, const u8 *data, 307 struct ice_sq_cd *cd); 308 bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw); 309 #endif /* _ICE_COMMON_H_ */ 310