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Searched refs:ENABLE_L1_TLB (Results 1 – 25 of 40) sorted by relevance

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/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Dgfxhub_v1_0.c161 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v1_0_init_tlb_regs()
358 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gfxhub_v1_0_gart_disable()
Dgfxhub_v2_0.c193 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v2_0_init_tlb_regs()
374 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gfxhub_v2_0_gart_disable()
Dgfxhub_v3_0_3.c196 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v3_0_3_init_tlb_regs()
386 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gfxhub_v3_0_3_gart_disable()
Dgfxhub_v3_0.c191 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v3_0_init_tlb_regs()
393 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gfxhub_v3_0_gart_disable()
Dgfxhub_v12_0.c199 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v12_0_init_tlb_regs()
401 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gfxhub_v12_0_gart_disable()
Dmmhub_v3_0_2.c209 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v3_0_2_init_tlb_regs()
403 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in mmhub_v3_0_2_gart_disable()
Dgfxhub_v11_5_0.c194 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v11_5_0_init_tlb_regs()
396 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gfxhub_v11_5_0_gart_disable()
Dmmhub_v3_0_1.c216 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v3_0_1_init_tlb_regs()
398 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in mmhub_v3_0_1_gart_disable()
Dmmhub_v2_0.c262 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v2_0_init_tlb_regs()
455 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in mmhub_v2_0_gart_disable()
Dmmhub_v2_3.c192 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v2_3_init_tlb_regs()
387 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in mmhub_v2_3_gart_disable()
Dmmhub_v3_3.c212 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v3_3_init_tlb_regs()
444 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in mmhub_v3_3_gart_disable()
Dmmhub_v3_0.c217 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v3_0_init_tlb_regs()
411 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in mmhub_v3_0_gart_disable()
Dmmhub_v4_1_0.c218 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v4_1_0_init_tlb_regs()
412 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in mmhub_v4_1_0_gart_disable()
Dmmhub_v1_8.c201 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, in mmhub_v1_8_init_tlb_regs()
447 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, in mmhub_v1_8_gart_disable()
Dgfxhub_v1_2.c205 ENABLE_L1_TLB, 1); in gfxhub_v1_2_xcc_init_tlb_regs()
453 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gfxhub_v1_2_xcc_gart_disable()
Dmmhub_v1_0.c144 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v1_0_init_tlb_regs()
354 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in mmhub_v1_0_gart_disable()
Dgfxhub_v2_1.c197 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v2_1_init_tlb_regs()
398 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gfxhub_v2_1_gart_disable()
Dgmc_v7_0.c614 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gmc_v7_0_gart_enable()
734 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gmc_v7_0_gart_disable()
Dmmhub_v1_7.c162 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v1_7_init_tlb_regs()
362 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in mmhub_v1_7_gart_disable()
Dgmc_v8_0.c829 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gmc_v8_0_gart_enable()
966 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gmc_v8_0_gart_disable()
Dmmhub_v9_4.c185 ENABLE_L1_TLB, 1); in mmhub_v9_4_init_tlb_regs()
424 ENABLE_L1_TLB, 0); in mmhub_v9_4_gart_disable()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hubp/dcn10/
Ddcn10_hubp.h409 HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, mask_sh),\
610 type ENABLE_L1_TLB;\
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hubp/dcn30/
Ddcn30_hubp.c64 ENABLE_L1_TLB, 1, in hubp3_set_vm_system_aperture_settings()
/linux-6.12.1/drivers/gpu/drm/radeon/
Drv770.c913 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | in rv770_pcie_gart_enable()
990 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | in rv770_agp_enable()
Drv770d.h465 #define ENABLE_L1_TLB (1 << 0) macro

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