Searched refs:Divider (Results 1 – 22 of 22) sorted by relevance
1 * Core Divider Clock bindings for Marvell MVEBU SoCs12 - reg : must be the register address of Core Divider control register
18 - reg : shall be the register address of the Core PLL and Clock Divider20 Core PLL and Clock Divider Control 1 register. Thus, it will have
157 uint8_t Divider; member
247 uint8_t Divider; member
758 pi->vce_level[i].Divider = (u8)dividers.post_div; in kv_populate_vce_table()821 pi->samu_level[i].Divider = (u8)dividers.post_div; in kv_populate_samu_table()880 pi->acp_level[i].Divider = (u8)dividers.post_div; in kv_populate_acp_table()
2670 table->VceLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_vce_level()2703 table->AcpLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_acp_level()2735 table->SamuLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_samu_level()
258 uint8_t Divider; member
205 uint8_t Divider; member
187 uint8_t Divider; member
198 uint8_t Divider; member
171 uint8_t Divider; member
213 uint8_t Divider; member
199 int Multiplier, Divider, Remainder; in ATIReduceRatio() local202 Divider = *Denominator; in ATIReduceRatio()204 while ((Remainder = Multiplier % Divider)) { in ATIReduceRatio()205 Multiplier = Divider; in ATIReduceRatio()206 Divider = Remainder; in ATIReduceRatio()209 *Numerator /= Divider; in ATIReduceRatio()210 *Denominator /= Divider; in ATIReduceRatio()
96 Voltage R1 R2 Divider Raw Value
990 pi->vce_level[i].Divider = (u8)dividers.post_div; in kv_populate_vce_table()1053 pi->samu_level[i].Divider = (u8)dividers.post_div; in kv_populate_samu_table()1112 pi->acp_level[i].Divider = (u8)dividers.post_div; in kv_populate_acp_table()
1449 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider; in fiji_populate_smc_vce_level()1485 table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider; in fiji_populate_smc_acp_level()
1407 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider; in polaris10_populate_smc_vce_level()1456 table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider; in polaris10_populate_smc_samu_level()
1583 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider; in ci_populate_smc_vce_level()1613 table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider; in ci_populate_smc_acp_level()
1405 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider; in tonga_populate_smc_vce_level()1449 table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider; in tonga_populate_smc_acp_level()
1236 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider; in vegam_populate_smc_vce_level()
231 bit 6-4 = Divider for clock