Searched refs:DWB_OGAM_CONTROL (Results 1 – 3 of 3) sorted by relevance
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dwb/dcn30/ |
D | dcn30_dwb_cm.c | 153 REG_GET_2(DWB_OGAM_CONTROL, in dwb3_get_ogam_current() 242 REG_SET(DWB_OGAM_CONTROL, 0, DWB_OGAM_MODE, 0); in dwb3_program_ogam_lut() 249 REG_SET(DWB_OGAM_CONTROL, 0, DWB_OGAM_MODE, 2); in dwb3_program_ogam_lut() 267 REG_UPDATE(DWB_OGAM_CONTROL, DWB_OGAM_SELECT, next_mode == LUT_RAM_A ? 0 : 1); in dwb3_program_ogam_lut()
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D | dcn30_dwb.h | 64 SR(DWB_OGAM_CONTROL),\ 211 SF_DWB2(DWB_OGAM_CONTROL, DWBCP, 0, DWB_OGAM_MODE, mask_sh),\ 212 SF_DWB2(DWB_OGAM_CONTROL, DWBCP, 0, DWB_OGAM_SELECT, mask_sh),\ 213 SF_DWB2(DWB_OGAM_CONTROL, DWBCP, 0, DWB_OGAM_PWL_DISABLE, mask_sh),\ 214 SF_DWB2(DWB_OGAM_CONTROL, DWBCP, 0, DWB_OGAM_MODE_CURRENT, mask_sh),\ 215 SF_DWB2(DWB_OGAM_CONTROL, DWBCP, 0, DWB_OGAM_SELECT_CURRENT, mask_sh),\ 776 uint32_t DWB_OGAM_CONTROL; member
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
D | dcn32_resource.h | 594 SR_ARR(DWB_GAMUT_REMAPB_C33_C34, id), SR_ARR(DWB_OGAM_CONTROL, id), \
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