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Searched refs:DPU_CLK_CTRL_DMA1 (Results 1 – 17 of 17) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/msm/disp/dpu1/catalog/
Ddpu_4_1_sdm670.h19 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
56 .clk_ctrl = DPU_CLK_CTRL_DMA1,
Ddpu_3_3_sdm630.h29 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
85 .clk_ctrl = DPU_CLK_CTRL_DMA1,
Ddpu_6_2_sc7180.h25 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
74 .clk_ctrl = DPU_CLK_CTRL_DMA1,
Ddpu_5_4_sm6125.h29 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
92 .clk_ctrl = DPU_CLK_CTRL_DMA1,
Ddpu_6_4_sm6350.h27 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
82 .clk_ctrl = DPU_CLK_CTRL_DMA1,
Ddpu_7_2_sc7280.h25 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
79 .clk_ctrl = DPU_CLK_CTRL_DMA1,
Ddpu_3_2_sdm660.h30 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
94 .clk_ctrl = DPU_CLK_CTRL_DMA1,
Ddpu_4_0_sdm845.h33 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
113 .clk_ctrl = DPU_CLK_CTRL_DMA1,
Ddpu_3_0_msm8998.h33 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
115 .clk_ctrl = DPU_CLK_CTRL_DMA1,
Ddpu_5_2_sm7150.h31 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
103 .clk_ctrl = DPU_CLK_CTRL_DMA1,
Ddpu_7_0_sm8350.h30 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
121 .clk_ctrl = DPU_CLK_CTRL_DMA1,
Ddpu_5_0_sm8150.h33 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
123 .clk_ctrl = DPU_CLK_CTRL_DMA1,
Ddpu_6_0_sm8250.h30 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
121 .clk_ctrl = DPU_CLK_CTRL_DMA1,
Ddpu_5_1_sc8180x.h33 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
122 .clk_ctrl = DPU_CLK_CTRL_DMA1,
Ddpu_8_1_sm8450.h31 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
122 .clk_ctrl = DPU_CLK_CTRL_DMA1,
Ddpu_8_0_sc8280xp.h31 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
121 .clk_ctrl = DPU_CLK_CTRL_DMA1,
/linux-6.12.1/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_catalog.h445 DPU_CLK_CTRL_DMA1, enumerator