Searched refs:DPMTABLE_OD_UPDATE_MCLK (Results 1 – 12 of 12) sorted by relevance
188 #define DPMTABLE_OD_UPDATE_MCLK 0x00000002 macro
1428 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { in ci_unfreeze_sclk_mclk_dpm()1536 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { in ci_freeze_sclk_mclk_dpm()3846 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; in ci_find_dpm_states_clocks_in_dpm_table()3869 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) in ci_populate_and_upload_sclk_mclk_dpm_levels()3878 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) { in ci_populate_and_upload_sclk_mclk_dpm_levels()4729 if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) in ci_update_and_upload_mc_reg_table()
175 #define DPMTABLE_OD_UPDATE_MCLK 0x00000002 macro
229 #define DPMTABLE_OD_UPDATE_MCLK 0x00000002 macro
1030 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; in smu7_check_dpm_table_updated()1040 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_MCLK; in smu7_check_dpm_table_updated()1055 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK; in smu7_check_dpm_table_updated()4126 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; in smu7_find_dpm_states_clocks_in_dpm_table()4234 DPMTABLE_OD_UPDATE_MCLK)) { in smu7_freeze_sclk_mclk_dpm()4269 if (hwmgr->od_enabled && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) { in smu7_populate_and_upload_sclk_mclk_dpm_levels()4285 (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) { in smu7_populate_and_upload_sclk_mclk_dpm_levels()4390 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { in smu7_unfreeze_sclk_mclk_dpm()4749 DPMTABLE_OD_UPDATE_MCLK | in smu7_check_states_equal()
1840 if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_MCLK) { in vega10_populate_single_memory_level()2542 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_MCLK; in vega10_check_dpm_table_updated()2585 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK; in vega10_init_smc_table()3470 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; in vega10_find_dpm_states_clocks_in_dpm_table()3500 if (hwmgr->od_enabled && data->need_update_dpm_table & DPMTABLE_OD_UPDATE_MCLK) { in vega10_populate_and_upload_sclk_mclk_dpm_levels()3514 (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) { in vega10_populate_and_upload_sclk_mclk_dpm_levels()5619 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; in vega10_odn_edit_dpm_table()
377 #define DPMTABLE_OD_UPDATE_MCLK 0x00000002 macro
1782 if (0 == (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) in iceland_update_and_upload_mc_reg_table()2168 (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK)) in iceland_program_mem_timing_parameters()
1817 if (0 == (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) in ci_update_and_upload_mc_reg_table()2205 (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK)) in ci_program_mem_timing_parameters()
2161 if (0 == (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) in tonga_update_and_upload_mc_reg_table()2557 (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK)) in tonga_program_mem_timing_parameters()
2255 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK)) in fiji_program_mem_timing_parameters()
2139 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK)) in polaris10_program_mem_timing_parameters()