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Searched refs:DPIO_PHY1 (Results 1 – 9 of 9) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/i915/
Dintel_gvt_mmio_table.c1132 MMIO_D(BXT_PHY_CTL_FAMILY(DPIO_PHY1)); in iterate_bxt_mmio()
1148 MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1)); in iterate_bxt_mmio()
1149 MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1)); in iterate_bxt_mmio()
1150 MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1)); in iterate_bxt_mmio()
1151 MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1)); in iterate_bxt_mmio()
1152 MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1)); in iterate_bxt_mmio()
1153 MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1)); in iterate_bxt_mmio()
1154 MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1)); in iterate_bxt_mmio()
1155 MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1)); in iterate_bxt_mmio()
1156 MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1)); in iterate_bxt_mmio()
[all …]
/linux-6.12.1/drivers/gpu/drm/i915/display/
Dintel_display_power_well.c1337 if (!dev_priv->display.power.chv_phy_assert[DPIO_PHY1]) in assert_chv_phy_status()
1338 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) | in assert_chv_phy_status()
1339 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) | in assert_chv_phy_status()
1340 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1)); in assert_chv_phy_status()
1384 phy_status |= PHY_POWERGOOD(DPIO_PHY1); in assert_chv_phy_status()
1387 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0) in assert_chv_phy_status()
1388 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0); in assert_chv_phy_status()
1391 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0))) in assert_chv_phy_status()
1392 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0); in assert_chv_phy_status()
1395 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0))) in assert_chv_phy_status()
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Dintel_dpio_phy.c169 .rcomp_phy = DPIO_PHY1,
177 [DPIO_PHY1] = {
191 .rcomp_phy = DPIO_PHY1,
199 [DPIO_PHY1] = {
211 .rcomp_phy = DPIO_PHY1,
684 return DPIO_PHY1; in vlv_dig_port_to_phy()
698 return DPIO_PHY1; in vlv_pipe_to_phy()
Dintel_dpio_phy.h25 DPIO_PHY1, enumerator
Dintel_display_power.c1758 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) | in chv_phy_control_init()
1761 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0); in chv_phy_control_init()
1811 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0); in chv_phy_control_init()
1814 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0); in chv_phy_control_init()
1816 dev_priv->display.power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1); in chv_phy_control_init()
1818 dev_priv->display.power.chv_phy_assert[DPIO_PHY1] = false; in chv_phy_control_init()
1820 dev_priv->display.power.chv_phy_assert[DPIO_PHY1] = true; in chv_phy_control_init()
Dintel_display_power_map.c478 .bxt.phy = DPIO_PHY1,
581 .bxt.phy = DPIO_PHY1,
/linux-6.12.1/drivers/gpu/drm/i915/gvt/
Dmmio.c268 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &= in intel_vgpu_reset_mmio()
272 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &= in intel_vgpu_reset_mmio()
Ddisplay.c241 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &= in emulate_monitor_status_change()
244 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &= ~BIT(30); in emulate_monitor_status_change()
273 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |= in emulate_monitor_status_change()
275 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) |= in emulate_monitor_status_change()
Dhandlers.c553 phy = DPIO_PHY1; in bxt_vgpu_get_dp_bitrate()
1890 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &= in bxt_gt_disp_pwron_write()
1892 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |= in bxt_gt_disp_pwron_write()
2763 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT, in init_bxt_mmio_info()
2780 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT, in init_bxt_mmio_info()
2782 MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT, in init_bxt_mmio_info()