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Searched refs:DPIO_CH0 (Results 1 – 6 of 6) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/i915/
Dintel_gvt_mmio_table.c1157 MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0)); in iterate_bxt_mmio()
1158 MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0)); in iterate_bxt_mmio()
1159 MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0)); in iterate_bxt_mmio()
1160 MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0)); in iterate_bxt_mmio()
1161 MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0)); in iterate_bxt_mmio()
1162 MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0)); in iterate_bxt_mmio()
1163 MMIO_D(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0)); in iterate_bxt_mmio()
1164 MMIO_D(BXT_PORT_TX_DW2_LN(DPIO_PHY0, DPIO_CH0, 0)); in iterate_bxt_mmio()
1165 MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0)); in iterate_bxt_mmio()
1166 MMIO_D(BXT_PORT_TX_DW3_LN(DPIO_PHY0, DPIO_CH0, 0)); in iterate_bxt_mmio()
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/linux-6.12.1/drivers/gpu/drm/i915/display/
Dintel_display_power_well.c1330 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) | in assert_chv_phy_status()
1331 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) | in assert_chv_phy_status()
1332 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) | in assert_chv_phy_status()
1338 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) | in assert_chv_phy_status()
1339 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) | in assert_chv_phy_status()
1340 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1)); in assert_chv_phy_status()
1346 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0) in assert_chv_phy_status()
1347 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0); in assert_chv_phy_status()
1354 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) | in assert_chv_phy_status()
1356 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0); in assert_chv_phy_status()
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Dintel_dpio_phy.c173 [DPIO_CH0] = { .port = PORT_B },
183 [DPIO_CH0] = { .port = PORT_A },
196 [DPIO_CH0] = { .port = PORT_B },
206 [DPIO_CH0] = { .port = PORT_A },
216 [DPIO_CH0] = { .port = PORT_C },
254 if (port == phy_info->channel[DPIO_CH0].port) { in bxt_port_to_phy_channel()
256 *ch = DPIO_CH0; in bxt_port_to_phy_channel()
271 *ch = DPIO_CH0; in bxt_port_to_phy_channel()
668 return DPIO_CH0; in vlv_dig_port_to_channel()
710 return DPIO_CH0; in vlv_pipe_to_channel()
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Dintel_dpio_phy.h19 DPIO_CH0, enumerator
114 return DPIO_CH0; in vlv_dig_port_to_channel()
126 return DPIO_CH0; in vlv_pipe_to_channel()
Dintel_display_power.c1759 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) | in chv_phy_control_init()
1761 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0); in chv_phy_control_init()
1779 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0); in chv_phy_control_init()
1782 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0); in chv_phy_control_init()
1811 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0); in chv_phy_control_init()
1814 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0); in chv_phy_control_init()
/linux-6.12.1/drivers/gpu/drm/i915/gvt/
Dhandlers.c546 enum dpio_channel ch = DPIO_CH0; in bxt_vgpu_get_dp_bitrate()
554 ch = DPIO_CH0; in bxt_vgpu_get_dp_bitrate()
558 ch = DPIO_CH0; in bxt_vgpu_get_dp_bitrate()
2772 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT, in init_bxt_mmio_info()
2774 MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT, in init_bxt_mmio_info()
2780 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT, in init_bxt_mmio_info()
2782 MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT, in init_bxt_mmio_info()