Searched refs:DPG_PIPE_LATENCY_CONTROL (Results 1 – 5 of 5) sorted by relevance
799 #define DPG_PIPE_LATENCY_CONTROL 0x6ccc macro
870 #define DPG_PIPE_LATENCY_CONTROL 0x6ccc macro
2416 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset, in dce6_program_watermarks()2424 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset, in dce6_program_watermarks()
9337 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset, in dce8_program_watermarks()9345 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset, in dce8_program_watermarks()
802 #define DPG_PIPE_LATENCY_CONTROL 0x1B33 macro