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Searched refs:DML2_MAX_PLANES (Results 1 – 16 of 16) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/
Ddml2_core_shared_types.h255 enum dml2_dram_clock_change_support DRAMClockChangeSupport[DML2_MAX_PLANES];
256 enum dml2_fclock_change_support FCLKChangeSupport[DML2_MAX_PLANES];
272 …bool MPCCombineEnable[DML2_MAX_PLANES]; /// <brief Indicate if the MPC Combine enable in the given…
273 …enum dml2_odm_mode ODMMode[DML2_MAX_PLANES]; /// <brief ODM mode that is chosen in the mode check …
274 …unsigned int DPPPerSurface[DML2_MAX_PLANES]; /// <brief How many DPPs are needed drive the surface…
275 …bool DSCEnabled[DML2_MAX_PLANES]; /// <brief Indicate if the DSC is actually required; used in mod…
276 bool FECEnabled[DML2_MAX_PLANES]; /// <brief Indicate if the FEC is actually required
277 …unsigned int NumberOfDSCSlices[DML2_MAX_PLANES]; /// <brief Indicate how many slices needed to sup…
279 double OutputBpp[DML2_MAX_PLANES];
280 enum dml2_core_internal_output_type OutputType[DML2_MAX_PLANES];
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Ddml2_core_utils.c259 for (unsigned int k = 0; k < DML2_MAX_PLANES; ++k) { in dml2_core_utils_pipe_plane_mapping()
263 for (unsigned int plane_idx = 0; plane_idx < DML2_MAX_PLANES; plane_idx++) { in dml2_core_utils_pipe_plane_mapping()
462 memset(scratch->main_stream_index_from_svp_stream_index, 0, sizeof(int) * DML2_MAX_PLANES); in dml2_core_utils_expand_implict_subvp()
463 memset(scratch->svp_stream_index_from_main_stream_index, 0, sizeof(int) * DML2_MAX_PLANES); in dml2_core_utils_expand_implict_subvp()
464 memset(scratch->main_plane_index_to_phantom_plane_index, 0, sizeof(int) * DML2_MAX_PLANES); in dml2_core_utils_expand_implict_subvp()
Ddml2_core_dcn4.c196 memset(scratch->main_stream_index_from_svp_stream_index, 0, sizeof(int) * DML2_MAX_PLANES); in expand_implict_subvp()
197 memset(scratch->svp_stream_index_from_main_stream_index, 0, sizeof(int) * DML2_MAX_PLANES); in expand_implict_subvp()
198 memset(scratch->main_plane_index_to_phantom_plane_index, 0, sizeof(int) * DML2_MAX_PLANES); in expand_implict_subvp()
Ddml2_core_dcn4_calcs.c220 for (unsigned int k = 0; k < DML2_MAX_PLANES; ++k) { in dml_calc_pipe_plane_mapping()
224 for (unsigned int plane_idx = 0; plane_idx < DML2_MAX_PLANES; plane_idx++) { in dml_calc_pipe_plane_mapping()
1030 bool DETPieceAssignedToThisSurfaceAlready[DML2_MAX_PLANES]; in CalculateDETBufferSize()
3541 double DCFClkDeepSleepPerSurface[DML2_MAX_PLANES]; in CalculateDCFCLKDeepSleep()
3656 unsigned int MaximumSwathHeightY[DML2_MAX_PLANES] = { 0 }; in CalculateSwathAndDETConfiguration()
3657 unsigned int MaximumSwathHeightC[DML2_MAX_PLANES] = { 0 }; in CalculateSwathAndDETConfiguration()
3658 unsigned int RoundedUpSwathSizeBytesY[DML2_MAX_PLANES] = { 0 }; in CalculateSwathAndDETConfiguration()
3659 unsigned int RoundedUpSwathSizeBytesC[DML2_MAX_PLANES] = { 0 }; in CalculateSwathAndDETConfiguration()
3660 unsigned int SwathWidthSingleDPP[DML2_MAX_PLANES] = { 0 }; in CalculateSwathAndDETConfiguration()
3661 unsigned int SwathWidthSingleDPPChroma[DML2_MAX_PLANES] = { 0 }; in CalculateSwathAndDETConfiguration()
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Ddml2_core_shared.c3015 for (unsigned int k = 0; k < DML2_MAX_PLANES; ++k) { in dml_calc_pipe_plane_mapping()
3019 for (unsigned int plane_idx = 0; plane_idx < DML2_MAX_PLANES; plane_idx++) { in dml_calc_pipe_plane_mapping()
3697 bool DETPieceAssignedToThisSurfaceAlready[DML2_MAX_PLANES]; in CalculateDETBufferSize()
3705 unsigned int TotalBandwidthPerStream[DML2_MAX_PLANES] = { 0 }; in CalculateDETBufferSize()
3707 unsigned int DETBudgetPerStream[DML2_MAX_PLANES] = { 0 }; in CalculateDETBufferSize()
3708 unsigned int RemainingDETBudgetPerStream[DML2_MAX_PLANES] = { 0 }; in CalculateDETBufferSize()
6207 double DCFClkDeepSleepPerSurface[DML2_MAX_PLANES]; in CalculateDCFCLKDeepSleep()
11616 dml2_assert(l->plane_idx < DML2_MAX_PLANES); in rq_dlg_get_dlg_reg()
11631 if (l->plane_idx < DML2_MAX_PLANES) { in rq_dlg_get_dlg_reg()
11666 l->first_pipe_idx_in_plane = DML2_MAX_PLANES; in rq_dlg_get_dlg_reg()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/
Ddml_top_types.h250 struct dml2_dchub_per_pipe_register_set *pipe_regs[DML2_MAX_PLANES];
255 struct dml2_dchub_per_pipe_register_set *pipe_regs[DML2_MAX_PLANES];
342 enum dml2_fclock_change_support FCLKChangeSupport[DML2_MAX_PLANES];
352 …bool MPCCombineEnable[DML2_MAX_PLANES]; /// <brief Indicate if the MPC Combine enable in the given…
353 …enum dml2_odm_mode ODMMode[DML2_MAX_PLANES]; /// <brief ODM mode that is chosen in the mode check …
354 …unsigned int DPPPerSurface[DML2_MAX_PLANES]; /// <brief How many DPPs are needed drive the surface…
355 …bool DSCEnabled[DML2_MAX_PLANES]; /// <brief Indicate if the DSC is actually required; used in mod…
356 bool FECEnabled[DML2_MAX_PLANES]; /// <brief Indicate if the FEC is actually required
357 …unsigned int NumberOfDSCSlices[DML2_MAX_PLANES]; /// <brief Indicate how many slices needed to sup…
358 double OutputBpp[DML2_MAX_PLANES];
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Ddml_top_display_cfg_types.h10 #define DML2_MAX_PLANES 8 macro
437 struct dml2_plane_parameters plane_descriptors[DML2_MAX_PLANES];
438 struct dml2_stream_parameters stream_descriptors[DML2_MAX_PLANES];
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/inc/
Ddml2_internal_shared_types.h175 struct core_stream_support_info stream_support_info[DML2_MAX_PLANES];
176 struct core_plane_support_info plane_support_info[DML2_MAX_PLANES];
215 } per_stream[DML2_MAX_PLANES];
221 } per_plane[DML2_MAX_PLANES];
240 bool per_plane_mcache_support[DML2_MAX_PLANES];
241 struct dml2_mcache_surface_allocation mcache_allocations[DML2_MAX_PLANES];
312 enum dml2_uclk_pstate_support_method pstate_switch_modes[DML2_MAX_PLANES];
315 struct dml2_implicit_svp_meta stream_svp_meta[DML2_MAX_PLANES];
319 struct dml2_fams2_meta stream_fams2_meta[DML2_MAX_PLANES];
458 int main_stream_index_from_svp_stream_index[DML2_MAX_PLANES];
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/inc/
Dcore_types.h536 struct dml2_mcache_surface_allocation mcache_allocations[DML2_MAX_PLANES];
538 struct dmub_fams2_stream_static_state fams2_stream_params[DML2_MAX_PLANES];
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/
Ddml2_pmo_dcn4_fams2.c547 enum dml2_pmo_pstate_method per_stream_variant_method[DML2_MAX_PLANES]; in expand_variant_strategy()
1012 for (i = 0; i < DML2_MAX_PLANES; i++) { in all_timings_support_drr()
1055 unsigned int num_planes_per_stream[DML2_MAX_PLANES] = { 0 }; in all_timings_support_svp()
1073 for (i = 0; i < DML2_MAX_PLANES; i++) { in all_timings_support_svp()
1123 for (i = 0; i < DML2_MAX_PLANES; i++) { in all_planes_match_method()
1257 memset(s->pmo_dcn4.sorted_group_gtl_disallow_index, 0, sizeof(unsigned int) * DML2_MAX_PLANES); in is_config_schedulable()
1538 for (i = 0; i < DML2_MAX_PLANES; i++) { in get_vactive_pstate_margin()
1553 for (i = 0; i < DML2_MAX_PLANES; i++) { in get_vactive_det_fill_latency_delay_us()
2024 sizeof(struct dml2_fams2_meta) * DML2_MAX_PLANES); in setup_display_config()
Ddml2_pmo_dcn3.c201 unsigned char remap_array[DML2_MAX_PLANES]; in are_timings_trivially_synchronizable()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/
Ddml2_top_optimization.c70 …rt, l->test_mcache.validate_admissibility_params.per_plane_status, sizeof(bool) * DML2_MAX_PLANES); in dml2_top_optimization_test_function_mcache()
Ddml_top_mcache.c348 …memset(params->per_plane_pipe_mcache_regs, 0, DML2_MAX_PLANES * DML2_MAX_DCN_PIPES * sizeof(struct… in dml2_top_mcache_build_mcache_programming()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/
Ddml2_dpmm_dcn4.c380 unsigned char remap_array[DML2_MAX_PLANES]; in are_timings_trivially_synchronizable()
418 unsigned char remap_array[DML2_MAX_PLANES]; in find_smallest_idle_time_in_vblank_us()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/dml21/
Ddml21_wrapper.c141 for (dml_prog_idx = 0; dml_prog_idx < DML2_MAX_PLANES; dml_prog_idx++) { in dml21_calculate_rq_and_dlg_params()
Ddml21_utils.c485 …tx.bw.dcn.fams2_stream_params, 0, sizeof(struct dmub_fams2_stream_static_state) * DML2_MAX_PLANES); in dml21_build_fams2_programming()