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Searched refs:DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK (Results 1 – 16 of 16) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_6_0_sh_mask.h5799 #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK 0x04000000L macro
Ddce_8_0_sh_mask.h7961 #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK 0x4000000 macro
Ddce_10_0_sh_mask.h6989 #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK 0x4000000 macro
Ddce_11_0_sh_mask.h6891 #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK 0x4000000 macro
Ddce_11_2_sh_mask.h7963 #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK 0x4000000 macro
Ddce_12_0_sh_mask.h4914 #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK … macro
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_0_3_sh_mask.h1536 #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK … macro
Ddcn_3_0_1_sh_mask.h2523 #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK … macro
Ddcn_2_1_0_sh_mask.h2382 #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK … macro
Ddcn_1_0_sh_mask.h3876 #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK … macro
Ddcn_3_1_2_sh_mask.h2019 #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK … macro
Ddcn_3_0_2_sh_mask.h2453 #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK … macro
Ddcn_3_1_6_sh_mask.h2584 #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK … macro
Ddcn_3_1_4_sh_mask.h10637 #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK … macro
Ddcn_2_0_0_sh_mask.h2650 #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK … macro
Ddcn_3_0_0_sh_mask.h2525 #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK … macro