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Searched refs:DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK (Results 1 – 16 of 16) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_6_0_sh_mask.h5791 #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK 0x01000000L macro
Ddce_8_0_sh_mask.h7953 #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK 0x1000000 macro
Ddce_10_0_sh_mask.h6981 #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK 0x1000000 macro
Ddce_11_0_sh_mask.h6883 #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK 0x1000000 macro
Ddce_11_2_sh_mask.h7955 #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK 0x1000000 macro
Ddce_12_0_sh_mask.h4910 #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK … macro
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_0_3_sh_mask.h1532 #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK … macro
Ddcn_3_0_1_sh_mask.h2519 #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK … macro
Ddcn_2_1_0_sh_mask.h2378 #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK … macro
Ddcn_1_0_sh_mask.h3872 #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK … macro
Ddcn_3_1_2_sh_mask.h2015 #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK … macro
Ddcn_3_0_2_sh_mask.h2449 #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK … macro
Ddcn_3_1_6_sh_mask.h2580 #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK … macro
Ddcn_3_1_4_sh_mask.h10633 #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK … macro
Ddcn_2_0_0_sh_mask.h2646 #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK … macro
Ddcn_3_0_0_sh_mask.h2521 #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK … macro