Searched refs:DMA_RB_CNTL (Results 1 – 12 of 12) sorted by relevance
/linux-6.12.1/drivers/gpu/drm/radeon/ |
D | ni_dma.c | 165 rb_cntl = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in cayman_dma_stop() 167 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, rb_cntl); in cayman_dma_stop() 170 rb_cntl = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in cayman_dma_stop() 172 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, rb_cntl); in cayman_dma_stop() 214 WREG32(DMA_RB_CNTL + reg_offset, rb_cntl); in cayman_dma_resume() 245 WREG32(DMA_RB_CNTL + reg_offset, rb_cntl | DMA_RB_ENABLE); in cayman_dma_resume()
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D | r600_dma.c | 100 u32 rb_cntl = RREG32(DMA_RB_CNTL); in r600_dma_stop() 106 WREG32(DMA_RB_CNTL, rb_cntl); in r600_dma_stop() 135 WREG32(DMA_RB_CNTL, rb_cntl); in r600_dma_resume() 169 WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE); in r600_dma_resume()
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D | ni.c | 1824 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in cayman_gpu_soft_reset() 1826 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); in cayman_gpu_soft_reset() 1831 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in cayman_gpu_soft_reset() 1833 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); in cayman_gpu_soft_reset()
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D | si.c | 3864 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in si_gpu_soft_reset() 3866 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); in si_gpu_soft_reset() 3870 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in si_gpu_soft_reset() 3872 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); in si_gpu_soft_reset() 4031 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in si_gpu_pci_config_reset() 4033 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); in si_gpu_pci_config_reset() 4035 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in si_gpu_pci_config_reset() 4037 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); in si_gpu_pci_config_reset()
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D | nid.h | 1304 #define DMA_RB_CNTL 0xd000 macro
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D | r600.c | 1708 tmp = RREG32(DMA_RB_CNTL); in r600_gpu_soft_reset() 1710 WREG32(DMA_RB_CNTL, tmp); in r600_gpu_soft_reset() 1839 tmp = RREG32(DMA_RB_CNTL); in r600_gpu_pci_config_reset() 1841 WREG32(DMA_RB_CNTL, tmp); in r600_gpu_pci_config_reset()
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D | evergreen.c | 3912 tmp = RREG32(DMA_RB_CNTL); in evergreen_gpu_soft_reset() 3914 WREG32(DMA_RB_CNTL, tmp); in evergreen_gpu_soft_reset() 4021 tmp = RREG32(DMA_RB_CNTL); in evergreen_gpu_pci_config_reset() 4023 WREG32(DMA_RB_CNTL, tmp); in evergreen_gpu_pci_config_reset()
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D | sid.h | 1815 #define DMA_RB_CNTL 0xd000 macro
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D | evergreend.h | 2618 #define DMA_RB_CNTL 0xd000 macro
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D | r600d.h | 613 #define DMA_RB_CNTL 0xd000 macro
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/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
D | si_dma.c | 120 rb_cntl = RREG32(DMA_RB_CNTL + sdma_offsets[i]); in si_dma_stop() 122 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl); in si_dma_stop() 145 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl); in si_dma_start() 173 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl | DMA_RB_ENABLE); in si_dma_start()
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D | sid.h | 1878 #define DMA_RB_CNTL 0x3400 macro
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