Searched refs:DMA_CNTL (Results 1 – 11 of 11) sorted by relevance
/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
D | si_dma.c | 167 dma_cntl = RREG32(DMA_CNTL + sdma_offsets[i]); in si_dma_start() 169 WREG32(DMA_CNTL + sdma_offsets[i], dma_cntl); in si_dma_start() 591 sdma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET); in si_dma_set_trap_irq_state() 593 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state() 596 sdma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET); in si_dma_set_trap_irq_state() 598 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state() 607 sdma_cntl = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET); in si_dma_set_trap_irq_state() 609 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state() 612 sdma_cntl = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET); in si_dma_set_trap_irq_state() 614 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()
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D | sid.h | 1897 #define DMA_CNTL 0x340b macro
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/linux-6.12.1/drivers/gpu/drm/radeon/ |
D | r600_dma.c | 159 dma_cntl = RREG32(DMA_CNTL); in r600_dma_resume() 161 WREG32(DMA_CNTL, dma_cntl); in r600_dma_resume()
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D | ni_dma.c | 238 dma_cntl = RREG32(DMA_CNTL + reg_offset); in cayman_dma_resume() 240 WREG32(DMA_CNTL + reg_offset, dma_cntl); in cayman_dma_resume()
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D | si.c | 5938 tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_disable_interrupt_state() 5939 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, tmp); in si_disable_interrupt_state() 5940 tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_disable_interrupt_state() 5941 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp); in si_disable_interrupt_state() 6054 dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_irq_set() 6055 dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_irq_set() 6087 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, dma_cntl); in si_irq_set() 6088 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, dma_cntl1); in si_irq_set()
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D | nid.h | 1323 #define DMA_CNTL 0xd02c macro
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D | r600.c | 3623 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; in r600_disable_interrupt_state() 3624 WREG32(DMA_CNTL, tmp); in r600_disable_interrupt_state() 3805 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE; in r600_irq_set() 3874 WREG32(DMA_CNTL, dma_cntl); in r600_irq_set()
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D | evergreen.c | 4471 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; in evergreen_disable_interrupt_state() 4472 WREG32(DMA_CNTL, tmp); in evergreen_disable_interrupt_state() 4518 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE; in evergreen_irq_set() 4567 WREG32(DMA_CNTL, dma_cntl); in evergreen_irq_set()
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D | sid.h | 1833 #define DMA_CNTL 0xd02c macro
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D | evergreend.h | 1404 #define DMA_CNTL 0xd02c macro
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D | r600d.h | 631 #define DMA_CNTL 0xd02c macro
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