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Searched refs:DISP_CC_MDSS_CORE_INT2_BCR (Results 1 – 9 of 9) sorted by relevance

/linux-6.12.1/include/dt-bindings/clock/
Dqcom,sm4450-dispcc.h48 #define DISP_CC_MDSS_CORE_INT2_BCR 1 macro
Dqcom,x1e80100-dispcc.h91 #define DISP_CC_MDSS_CORE_INT2_BCR 1 macro
Dqcom,sm8550-dispcc.h94 #define DISP_CC_MDSS_CORE_INT2_BCR 1 macro
Dqcom,sm8650-dispcc.h94 #define DISP_CC_MDSS_CORE_INT2_BCR 1 macro
Dqcom,sm8450-dispcc.h96 #define DISP_CC_MDSS_CORE_INT2_BCR 1 macro
/linux-6.12.1/drivers/clk/qcom/
Ddispcc-sm4450.c713 [DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 },
Ddispcc-x1e80100.c1621 [DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 },
Ddispcc-sm8450.c1720 [DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 },
Ddispcc-sm8550.c1725 [DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 },