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Searched refs:DFH (Results 1 – 3 of 3) sorted by relevance

/linux-6.12.1/drivers/fpga/
Ddfl.h63 #define DFH 0x0 macro
122 #define FME_HDR_DFH DFH
163 #define PORT_HDR_DFH DFH
448 u64 v = readq(base + DFH); in dfl_feature_is_fme()
456 u64 v = readq(base + DFH); in dfl_feature_is_port()
464 return (u8)FIELD_GET(DFH_REVISION, readq(base + DFH)); in dfl_feature_revision()
Ddfl.c1294 v = readq(binfo->ioaddr + DFH); in parse_feature_fiu()
1344 v = readq(binfo->ioaddr + ofst + DFH); in parse_feature()
1385 v = readq(binfo->ioaddr + start - binfo->start + DFH); in parse_feature_list()
/linux-6.12.1/Documentation/fpga/
Ddfl.rst85 |63 Type 60|59 DFH VER 52|51 Rsvd 41|40 EOL|39 Next 16|15 REV 12|11 ID 0| 0x00
94 * Type - The type of DFH (e.g. FME, AFU, or private feature).
95 * DFH VER - The version of the DFH.
97 * EOL - Set if the DFH is the end of the Device Feature List (DFL).
98 * Next - The offset in bytes of the next DFH in the DFL from the DFH start,
99 and the start of a DFH must be aligned to an 8 byte boundary.
122 * Decouples the DFH location from the register space of the feature itself.
125 The format of Version 1 of the Device Feature Header (DFH) is shown below::
128 |63 Type 60|59 DFH VER 52|51 Rsvd 41|40 EOL|39 Next 16|15 REV 12|11 ID 0| 0x00
153 * Type - The type of DFH (e.g. FME, AFU, or private feature).
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