1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * tps65910.h -- TI TPS6591x 4 * 5 * Copyright 2010-2011 Texas Instruments Inc. 6 * 7 * Author: Graeme Gregory <gg@slimlogic.co.uk> 8 * Author: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk> 9 * Author: Arnaud Deconinck <a-deconinck@ti.com> 10 */ 11 12 #ifndef __LINUX_MFD_TPS65910_H 13 #define __LINUX_MFD_TPS65910_H 14 15 #include <linux/gpio.h> 16 #include <linux/regmap.h> 17 18 /* TPS chip id list */ 19 #define TPS65910 0 20 #define TPS65911 1 21 22 /* TPS regulator type list */ 23 #define REGULATOR_LDO 0 24 #define REGULATOR_DCDC 1 25 26 /* 27 * List of registers for component TPS65910 28 * 29 */ 30 31 #define TPS65910_SECONDS 0x0 32 #define TPS65910_MINUTES 0x1 33 #define TPS65910_HOURS 0x2 34 #define TPS65910_DAYS 0x3 35 #define TPS65910_MONTHS 0x4 36 #define TPS65910_YEARS 0x5 37 #define TPS65910_WEEKS 0x6 38 #define TPS65910_ALARM_SECONDS 0x8 39 #define TPS65910_ALARM_MINUTES 0x9 40 #define TPS65910_ALARM_HOURS 0xA 41 #define TPS65910_ALARM_DAYS 0xB 42 #define TPS65910_ALARM_MONTHS 0xC 43 #define TPS65910_ALARM_YEARS 0xD 44 #define TPS65910_RTC_CTRL 0x10 45 #define TPS65910_RTC_STATUS 0x11 46 #define TPS65910_RTC_INTERRUPTS 0x12 47 #define TPS65910_RTC_COMP_LSB 0x13 48 #define TPS65910_RTC_COMP_MSB 0x14 49 #define TPS65910_RTC_RES_PROG 0x15 50 #define TPS65910_RTC_RESET_STATUS 0x16 51 #define TPS65910_BCK1 0x17 52 #define TPS65910_BCK2 0x18 53 #define TPS65910_BCK3 0x19 54 #define TPS65910_BCK4 0x1A 55 #define TPS65910_BCK5 0x1B 56 #define TPS65910_PUADEN 0x1C 57 #define TPS65910_REF 0x1D 58 #define TPS65910_VRTC 0x1E 59 #define TPS65910_VIO 0x20 60 #define TPS65910_VDD1 0x21 61 #define TPS65910_VDD1_OP 0x22 62 #define TPS65910_VDD1_SR 0x23 63 #define TPS65910_VDD2 0x24 64 #define TPS65910_VDD2_OP 0x25 65 #define TPS65910_VDD2_SR 0x26 66 #define TPS65910_VDD3 0x27 67 #define TPS65910_VDIG1 0x30 68 #define TPS65910_VDIG2 0x31 69 #define TPS65910_VAUX1 0x32 70 #define TPS65910_VAUX2 0x33 71 #define TPS65910_VAUX33 0x34 72 #define TPS65910_VMMC 0x35 73 #define TPS65910_VPLL 0x36 74 #define TPS65910_VDAC 0x37 75 #define TPS65910_THERM 0x38 76 #define TPS65910_BBCH 0x39 77 #define TPS65910_DCDCCTRL 0x3E 78 #define TPS65910_DEVCTRL 0x3F 79 #define TPS65910_DEVCTRL2 0x40 80 #define TPS65910_SLEEP_KEEP_LDO_ON 0x41 81 #define TPS65910_SLEEP_KEEP_RES_ON 0x42 82 #define TPS65910_SLEEP_SET_LDO_OFF 0x43 83 #define TPS65910_SLEEP_SET_RES_OFF 0x44 84 #define TPS65910_EN1_LDO_ASS 0x45 85 #define TPS65910_EN1_SMPS_ASS 0x46 86 #define TPS65910_EN2_LDO_ASS 0x47 87 #define TPS65910_EN2_SMPS_ASS 0x48 88 #define TPS65910_EN3_LDO_ASS 0x49 89 #define TPS65910_SPARE 0x4A 90 #define TPS65910_INT_STS 0x50 91 #define TPS65910_INT_MSK 0x51 92 #define TPS65910_INT_STS2 0x52 93 #define TPS65910_INT_MSK2 0x53 94 #define TPS65910_INT_STS3 0x54 95 #define TPS65910_INT_MSK3 0x55 96 #define TPS65910_GPIO0 0x60 97 #define TPS65910_GPIO1 0x61 98 #define TPS65910_GPIO2 0x62 99 #define TPS65910_GPIO3 0x63 100 #define TPS65910_GPIO4 0x64 101 #define TPS65910_GPIO5 0x65 102 #define TPS65910_GPIO6 0x66 103 #define TPS65910_GPIO7 0x67 104 #define TPS65910_GPIO8 0x68 105 #define TPS65910_JTAGVERNUM 0x80 106 #define TPS65910_MAX_REGISTER 0x80 107 108 /* 109 * List of registers specific to TPS65911 110 */ 111 #define TPS65911_VDDCTRL 0x27 112 #define TPS65911_VDDCTRL_OP 0x28 113 #define TPS65911_VDDCTRL_SR 0x29 114 #define TPS65911_LDO1 0x30 115 #define TPS65911_LDO2 0x31 116 #define TPS65911_LDO5 0x32 117 #define TPS65911_LDO8 0x33 118 #define TPS65911_LDO7 0x34 119 #define TPS65911_LDO6 0x35 120 #define TPS65911_LDO4 0x36 121 #define TPS65911_LDO3 0x37 122 #define TPS65911_VMBCH 0x6A 123 #define TPS65911_VMBCH2 0x6B 124 125 /* 126 * List of register bitfields for component TPS65910 127 * 128 */ 129 130 /* RTC_CTRL_REG bitfields */ 131 #define TPS65910_RTC_CTRL_STOP_RTC 0x01 /*0=stop, 1=run */ 132 #define TPS65910_RTC_CTRL_AUTO_COMP 0x04 133 #define TPS65910_RTC_CTRL_GET_TIME 0x40 134 135 /* RTC_STATUS_REG bitfields */ 136 #define TPS65910_RTC_STATUS_ALARM 0x40 137 138 /* RTC_INTERRUPTS_REG bitfields */ 139 #define TPS65910_RTC_INTERRUPTS_EVERY 0x03 140 #define TPS65910_RTC_INTERRUPTS_IT_ALARM 0x08 141 142 /*Register BCK1 (0x80) register.RegisterDescription */ 143 #define BCK1_BCKUP_MASK 0xFF 144 #define BCK1_BCKUP_SHIFT 0 145 146 147 /*Register BCK2 (0x80) register.RegisterDescription */ 148 #define BCK2_BCKUP_MASK 0xFF 149 #define BCK2_BCKUP_SHIFT 0 150 151 152 /*Register BCK3 (0x80) register.RegisterDescription */ 153 #define BCK3_BCKUP_MASK 0xFF 154 #define BCK3_BCKUP_SHIFT 0 155 156 157 /*Register BCK4 (0x80) register.RegisterDescription */ 158 #define BCK4_BCKUP_MASK 0xFF 159 #define BCK4_BCKUP_SHIFT 0 160 161 162 /*Register BCK5 (0x80) register.RegisterDescription */ 163 #define BCK5_BCKUP_MASK 0xFF 164 #define BCK5_BCKUP_SHIFT 0 165 166 167 /*Register PUADEN (0x80) register.RegisterDescription */ 168 #define PUADEN_EN3P_MASK 0x80 169 #define PUADEN_EN3P_SHIFT 7 170 #define PUADEN_I2CCTLP_MASK 0x40 171 #define PUADEN_I2CCTLP_SHIFT 6 172 #define PUADEN_I2CSRP_MASK 0x20 173 #define PUADEN_I2CSRP_SHIFT 5 174 #define PUADEN_PWRONP_MASK 0x10 175 #define PUADEN_PWRONP_SHIFT 4 176 #define PUADEN_SLEEPP_MASK 0x08 177 #define PUADEN_SLEEPP_SHIFT 3 178 #define PUADEN_PWRHOLDP_MASK 0x04 179 #define PUADEN_PWRHOLDP_SHIFT 2 180 #define PUADEN_BOOT1P_MASK 0x02 181 #define PUADEN_BOOT1P_SHIFT 1 182 #define PUADEN_BOOT0P_MASK 0x01 183 #define PUADEN_BOOT0P_SHIFT 0 184 185 186 /*Register REF (0x80) register.RegisterDescription */ 187 #define REF_VMBCH_SEL_MASK 0x0C 188 #define REF_VMBCH_SEL_SHIFT 2 189 #define REF_ST_MASK 0x03 190 #define REF_ST_SHIFT 0 191 192 193 /*Register VRTC (0x80) register.RegisterDescription */ 194 #define VRTC_VRTC_OFFMASK_MASK 0x08 195 #define VRTC_VRTC_OFFMASK_SHIFT 3 196 #define VRTC_ST_MASK 0x03 197 #define VRTC_ST_SHIFT 0 198 199 200 /*Register VIO (0x80) register.RegisterDescription */ 201 #define VIO_ILMAX_MASK 0xC0 202 #define VIO_ILMAX_SHIFT 6 203 #define VIO_SEL_MASK 0x0C 204 #define VIO_SEL_SHIFT 2 205 #define VIO_ST_MASK 0x03 206 #define VIO_ST_SHIFT 0 207 208 209 /*Register VDD1 (0x80) register.RegisterDescription */ 210 #define VDD1_VGAIN_SEL_MASK 0xC0 211 #define VDD1_VGAIN_SEL_SHIFT 6 212 #define VDD1_ILMAX_MASK 0x20 213 #define VDD1_ILMAX_SHIFT 5 214 #define VDD1_TSTEP_MASK 0x1C 215 #define VDD1_TSTEP_SHIFT 2 216 #define VDD1_ST_MASK 0x03 217 #define VDD1_ST_SHIFT 0 218 219 220 /*Register VDD1_OP (0x80) register.RegisterDescription */ 221 #define VDD1_OP_CMD_MASK 0x80 222 #define VDD1_OP_CMD_SHIFT 7 223 #define VDD1_OP_SEL_MASK 0x7F 224 #define VDD1_OP_SEL_SHIFT 0 225 226 227 /*Register VDD1_SR (0x80) register.RegisterDescription */ 228 #define VDD1_SR_SEL_MASK 0x7F 229 #define VDD1_SR_SEL_SHIFT 0 230 231 232 /*Register VDD2 (0x80) register.RegisterDescription */ 233 #define VDD2_VGAIN_SEL_MASK 0xC0 234 #define VDD2_VGAIN_SEL_SHIFT 6 235 #define VDD2_ILMAX_MASK 0x20 236 #define VDD2_ILMAX_SHIFT 5 237 #define VDD2_TSTEP_MASK 0x1C 238 #define VDD2_TSTEP_SHIFT 2 239 #define VDD2_ST_MASK 0x03 240 #define VDD2_ST_SHIFT 0 241 242 243 /*Register VDD2_OP (0x80) register.RegisterDescription */ 244 #define VDD2_OP_CMD_MASK 0x80 245 #define VDD2_OP_CMD_SHIFT 7 246 #define VDD2_OP_SEL_MASK 0x7F 247 #define VDD2_OP_SEL_SHIFT 0 248 249 /*Register VDD2_SR (0x80) register.RegisterDescription */ 250 #define VDD2_SR_SEL_MASK 0x7F 251 #define VDD2_SR_SEL_SHIFT 0 252 253 254 /*Registers VDD1, VDD2 voltage values definitions */ 255 #define VDD1_2_NUM_VOLT_FINE 73 256 #define VDD1_2_NUM_VOLT_COARSE 3 257 #define VDD1_2_MIN_VOLT 6000 258 #define VDD1_2_OFFSET 125 259 260 261 /*Register VDD3 (0x80) register.RegisterDescription */ 262 #define VDD3_CKINEN_MASK 0x04 263 #define VDD3_CKINEN_SHIFT 2 264 #define VDD3_ST_MASK 0x03 265 #define VDD3_ST_SHIFT 0 266 #define VDDCTRL_MIN_VOLT 6000 267 #define VDDCTRL_OFFSET 125 268 269 /*Registers VDIG (0x80) to VDAC register.RegisterDescription */ 270 #define LDO_SEL_MASK 0x0C 271 #define LDO_SEL_SHIFT 2 272 #define LDO_ST_MASK 0x03 273 #define LDO_ST_SHIFT 0 274 #define LDO_ST_ON_BIT 0x01 275 #define LDO_ST_MODE_BIT 0x02 276 277 278 /* Registers LDO1 to LDO8 in tps65910 */ 279 #define LDO1_SEL_MASK 0xFC 280 #define LDO3_SEL_MASK 0x7C 281 #define LDO_MIN_VOLT 1000 282 #define LDO_MAX_VOLT 3300 283 284 285 /*Register VDIG1 (0x80) register.RegisterDescription */ 286 #define VDIG1_SEL_MASK 0x0C 287 #define VDIG1_SEL_SHIFT 2 288 #define VDIG1_ST_MASK 0x03 289 #define VDIG1_ST_SHIFT 0 290 291 292 /*Register VDIG2 (0x80) register.RegisterDescription */ 293 #define VDIG2_SEL_MASK 0x0C 294 #define VDIG2_SEL_SHIFT 2 295 #define VDIG2_ST_MASK 0x03 296 #define VDIG2_ST_SHIFT 0 297 298 299 /*Register VAUX1 (0x80) register.RegisterDescription */ 300 #define VAUX1_SEL_MASK 0x0C 301 #define VAUX1_SEL_SHIFT 2 302 #define VAUX1_ST_MASK 0x03 303 #define VAUX1_ST_SHIFT 0 304 305 306 /*Register VAUX2 (0x80) register.RegisterDescription */ 307 #define VAUX2_SEL_MASK 0x0C 308 #define VAUX2_SEL_SHIFT 2 309 #define VAUX2_ST_MASK 0x03 310 #define VAUX2_ST_SHIFT 0 311 312 313 /*Register VAUX33 (0x80) register.RegisterDescription */ 314 #define VAUX33_SEL_MASK 0x0C 315 #define VAUX33_SEL_SHIFT 2 316 #define VAUX33_ST_MASK 0x03 317 #define VAUX33_ST_SHIFT 0 318 319 320 /*Register VMMC (0x80) register.RegisterDescription */ 321 #define VMMC_SEL_MASK 0x0C 322 #define VMMC_SEL_SHIFT 2 323 #define VMMC_ST_MASK 0x03 324 #define VMMC_ST_SHIFT 0 325 326 327 /*Register VPLL (0x80) register.RegisterDescription */ 328 #define VPLL_SEL_MASK 0x0C 329 #define VPLL_SEL_SHIFT 2 330 #define VPLL_ST_MASK 0x03 331 #define VPLL_ST_SHIFT 0 332 333 334 /*Register VDAC (0x80) register.RegisterDescription */ 335 #define VDAC_SEL_MASK 0x0C 336 #define VDAC_SEL_SHIFT 2 337 #define VDAC_ST_MASK 0x03 338 #define VDAC_ST_SHIFT 0 339 340 341 /*Register THERM (0x80) register.RegisterDescription */ 342 #define THERM_THERM_HD_MASK 0x20 343 #define THERM_THERM_HD_SHIFT 5 344 #define THERM_THERM_TS_MASK 0x10 345 #define THERM_THERM_TS_SHIFT 4 346 #define THERM_THERM_HDSEL_MASK 0x0C 347 #define THERM_THERM_HDSEL_SHIFT 2 348 #define THERM_RSVD1_MASK 0x02 349 #define THERM_RSVD1_SHIFT 1 350 #define THERM_THERM_STATE_MASK 0x01 351 #define THERM_THERM_STATE_SHIFT 0 352 353 354 /*Register BBCH (0x80) register.RegisterDescription */ 355 #define BBCH_BBSEL_MASK 0x06 356 #define BBCH_BBSEL_SHIFT 1 357 358 359 /*Register DCDCCTRL (0x80) register.RegisterDescription */ 360 #define DCDCCTRL_VDD2_PSKIP_MASK 0x20 361 #define DCDCCTRL_VDD2_PSKIP_SHIFT 5 362 #define DCDCCTRL_VDD1_PSKIP_MASK 0x10 363 #define DCDCCTRL_VDD1_PSKIP_SHIFT 4 364 #define DCDCCTRL_VIO_PSKIP_MASK 0x08 365 #define DCDCCTRL_VIO_PSKIP_SHIFT 3 366 #define DCDCCTRL_DCDCCKEXT_MASK 0x04 367 #define DCDCCTRL_DCDCCKEXT_SHIFT 2 368 #define DCDCCTRL_DCDCCKSYNC_MASK 0x03 369 #define DCDCCTRL_DCDCCKSYNC_SHIFT 0 370 371 372 /*Register DEVCTRL (0x80) register.RegisterDescription */ 373 #define DEVCTRL_PWR_OFF_MASK 0x80 374 #define DEVCTRL_PWR_OFF_SHIFT 7 375 #define DEVCTRL_RTC_PWDN_MASK 0x40 376 #define DEVCTRL_RTC_PWDN_SHIFT 6 377 #define DEVCTRL_CK32K_CTRL_MASK 0x20 378 #define DEVCTRL_CK32K_CTRL_SHIFT 5 379 #define DEVCTRL_SR_CTL_I2C_SEL_MASK 0x10 380 #define DEVCTRL_SR_CTL_I2C_SEL_SHIFT 4 381 #define DEVCTRL_DEV_OFF_RST_MASK 0x08 382 #define DEVCTRL_DEV_OFF_RST_SHIFT 3 383 #define DEVCTRL_DEV_ON_MASK 0x04 384 #define DEVCTRL_DEV_ON_SHIFT 2 385 #define DEVCTRL_DEV_SLP_MASK 0x02 386 #define DEVCTRL_DEV_SLP_SHIFT 1 387 #define DEVCTRL_DEV_OFF_MASK 0x01 388 #define DEVCTRL_DEV_OFF_SHIFT 0 389 390 391 /*Register DEVCTRL2 (0x80) register.RegisterDescription */ 392 #define DEVCTRL2_TSLOT_LENGTH_MASK 0x30 393 #define DEVCTRL2_TSLOT_LENGTH_SHIFT 4 394 #define DEVCTRL2_SLEEPSIG_POL_MASK 0x08 395 #define DEVCTRL2_SLEEPSIG_POL_SHIFT 3 396 #define DEVCTRL2_PWON_LP_OFF_MASK 0x04 397 #define DEVCTRL2_PWON_LP_OFF_SHIFT 2 398 #define DEVCTRL2_PWON_LP_RST_MASK 0x02 399 #define DEVCTRL2_PWON_LP_RST_SHIFT 1 400 #define DEVCTRL2_IT_POL_MASK 0x01 401 #define DEVCTRL2_IT_POL_SHIFT 0 402 403 404 /*Register SLEEP_KEEP_LDO_ON (0x80) register.RegisterDescription */ 405 #define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_MASK 0x80 406 #define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_SHIFT 7 407 #define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_MASK 0x40 408 #define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_SHIFT 6 409 #define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_MASK 0x20 410 #define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_SHIFT 5 411 #define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_MASK 0x10 412 #define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_SHIFT 4 413 #define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_MASK 0x08 414 #define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_SHIFT 3 415 #define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_MASK 0x04 416 #define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_SHIFT 2 417 #define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_MASK 0x02 418 #define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_SHIFT 1 419 #define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_MASK 0x01 420 #define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_SHIFT 0 421 422 423 /*Register SLEEP_KEEP_RES_ON (0x80) register.RegisterDescription */ 424 #define SLEEP_KEEP_RES_ON_THERM_KEEPON_MASK 0x80 425 #define SLEEP_KEEP_RES_ON_THERM_KEEPON_SHIFT 7 426 #define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_MASK 0x40 427 #define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_SHIFT 6 428 #define SLEEP_KEEP_RES_ON_VRTC_KEEPON_MASK 0x20 429 #define SLEEP_KEEP_RES_ON_VRTC_KEEPON_SHIFT 5 430 #define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_MASK 0x10 431 #define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_SHIFT 4 432 #define SLEEP_KEEP_RES_ON_VDD3_KEEPON_MASK 0x08 433 #define SLEEP_KEEP_RES_ON_VDD3_KEEPON_SHIFT 3 434 #define SLEEP_KEEP_RES_ON_VDD2_KEEPON_MASK 0x04 435 #define SLEEP_KEEP_RES_ON_VDD2_KEEPON_SHIFT 2 436 #define SLEEP_KEEP_RES_ON_VDD1_KEEPON_MASK 0x02 437 #define SLEEP_KEEP_RES_ON_VDD1_KEEPON_SHIFT 1 438 #define SLEEP_KEEP_RES_ON_VIO_KEEPON_MASK 0x01 439 #define SLEEP_KEEP_RES_ON_VIO_KEEPON_SHIFT 0 440 441 442 /*Register SLEEP_SET_LDO_OFF (0x80) register.RegisterDescription */ 443 #define SLEEP_SET_LDO_OFF_VDAC_SETOFF_MASK 0x80 444 #define SLEEP_SET_LDO_OFF_VDAC_SETOFF_SHIFT 7 445 #define SLEEP_SET_LDO_OFF_VPLL_SETOFF_MASK 0x40 446 #define SLEEP_SET_LDO_OFF_VPLL_SETOFF_SHIFT 6 447 #define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_MASK 0x20 448 #define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_SHIFT 5 449 #define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_MASK 0x10 450 #define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_SHIFT 4 451 #define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_MASK 0x08 452 #define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_SHIFT 3 453 #define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_MASK 0x04 454 #define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_SHIFT 2 455 #define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_MASK 0x02 456 #define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_SHIFT 1 457 #define SLEEP_SET_LDO_OFF_VMMC_SETOFF_MASK 0x01 458 #define SLEEP_SET_LDO_OFF_VMMC_SETOFF_SHIFT 0 459 460 461 /*Register SLEEP_SET_RES_OFF (0x80) register.RegisterDescription */ 462 #define SLEEP_SET_RES_OFF_DEFAULT_VOLT_MASK 0x80 463 #define SLEEP_SET_RES_OFF_DEFAULT_VOLT_SHIFT 7 464 #define SLEEP_SET_RES_OFF_RSVD_MASK 0x60 465 #define SLEEP_SET_RES_OFF_RSVD_SHIFT 5 466 #define SLEEP_SET_RES_OFF_SPARE_SETOFF_MASK 0x10 467 #define SLEEP_SET_RES_OFF_SPARE_SETOFF_SHIFT 4 468 #define SLEEP_SET_RES_OFF_VDD3_SETOFF_MASK 0x08 469 #define SLEEP_SET_RES_OFF_VDD3_SETOFF_SHIFT 3 470 #define SLEEP_SET_RES_OFF_VDD2_SETOFF_MASK 0x04 471 #define SLEEP_SET_RES_OFF_VDD2_SETOFF_SHIFT 2 472 #define SLEEP_SET_RES_OFF_VDD1_SETOFF_MASK 0x02 473 #define SLEEP_SET_RES_OFF_VDD1_SETOFF_SHIFT 1 474 #define SLEEP_SET_RES_OFF_VIO_SETOFF_MASK 0x01 475 #define SLEEP_SET_RES_OFF_VIO_SETOFF_SHIFT 0 476 477 478 /*Register EN1_LDO_ASS (0x80) register.RegisterDescription */ 479 #define EN1_LDO_ASS_VDAC_EN1_MASK 0x80 480 #define EN1_LDO_ASS_VDAC_EN1_SHIFT 7 481 #define EN1_LDO_ASS_VPLL_EN1_MASK 0x40 482 #define EN1_LDO_ASS_VPLL_EN1_SHIFT 6 483 #define EN1_LDO_ASS_VAUX33_EN1_MASK 0x20 484 #define EN1_LDO_ASS_VAUX33_EN1_SHIFT 5 485 #define EN1_LDO_ASS_VAUX2_EN1_MASK 0x10 486 #define EN1_LDO_ASS_VAUX2_EN1_SHIFT 4 487 #define EN1_LDO_ASS_VAUX1_EN1_MASK 0x08 488 #define EN1_LDO_ASS_VAUX1_EN1_SHIFT 3 489 #define EN1_LDO_ASS_VDIG2_EN1_MASK 0x04 490 #define EN1_LDO_ASS_VDIG2_EN1_SHIFT 2 491 #define EN1_LDO_ASS_VDIG1_EN1_MASK 0x02 492 #define EN1_LDO_ASS_VDIG1_EN1_SHIFT 1 493 #define EN1_LDO_ASS_VMMC_EN1_MASK 0x01 494 #define EN1_LDO_ASS_VMMC_EN1_SHIFT 0 495 496 497 /*Register EN1_SMPS_ASS (0x80) register.RegisterDescription */ 498 #define EN1_SMPS_ASS_RSVD_MASK 0xE0 499 #define EN1_SMPS_ASS_RSVD_SHIFT 5 500 #define EN1_SMPS_ASS_SPARE_EN1_MASK 0x10 501 #define EN1_SMPS_ASS_SPARE_EN1_SHIFT 4 502 #define EN1_SMPS_ASS_VDD3_EN1_MASK 0x08 503 #define EN1_SMPS_ASS_VDD3_EN1_SHIFT 3 504 #define EN1_SMPS_ASS_VDD2_EN1_MASK 0x04 505 #define EN1_SMPS_ASS_VDD2_EN1_SHIFT 2 506 #define EN1_SMPS_ASS_VDD1_EN1_MASK 0x02 507 #define EN1_SMPS_ASS_VDD1_EN1_SHIFT 1 508 #define EN1_SMPS_ASS_VIO_EN1_MASK 0x01 509 #define EN1_SMPS_ASS_VIO_EN1_SHIFT 0 510 511 512 /*Register EN2_LDO_ASS (0x80) register.RegisterDescription */ 513 #define EN2_LDO_ASS_VDAC_EN2_MASK 0x80 514 #define EN2_LDO_ASS_VDAC_EN2_SHIFT 7 515 #define EN2_LDO_ASS_VPLL_EN2_MASK 0x40 516 #define EN2_LDO_ASS_VPLL_EN2_SHIFT 6 517 #define EN2_LDO_ASS_VAUX33_EN2_MASK 0x20 518 #define EN2_LDO_ASS_VAUX33_EN2_SHIFT 5 519 #define EN2_LDO_ASS_VAUX2_EN2_MASK 0x10 520 #define EN2_LDO_ASS_VAUX2_EN2_SHIFT 4 521 #define EN2_LDO_ASS_VAUX1_EN2_MASK 0x08 522 #define EN2_LDO_ASS_VAUX1_EN2_SHIFT 3 523 #define EN2_LDO_ASS_VDIG2_EN2_MASK 0x04 524 #define EN2_LDO_ASS_VDIG2_EN2_SHIFT 2 525 #define EN2_LDO_ASS_VDIG1_EN2_MASK 0x02 526 #define EN2_LDO_ASS_VDIG1_EN2_SHIFT 1 527 #define EN2_LDO_ASS_VMMC_EN2_MASK 0x01 528 #define EN2_LDO_ASS_VMMC_EN2_SHIFT 0 529 530 531 /*Register EN2_SMPS_ASS (0x80) register.RegisterDescription */ 532 #define EN2_SMPS_ASS_RSVD_MASK 0xE0 533 #define EN2_SMPS_ASS_RSVD_SHIFT 5 534 #define EN2_SMPS_ASS_SPARE_EN2_MASK 0x10 535 #define EN2_SMPS_ASS_SPARE_EN2_SHIFT 4 536 #define EN2_SMPS_ASS_VDD3_EN2_MASK 0x08 537 #define EN2_SMPS_ASS_VDD3_EN2_SHIFT 3 538 #define EN2_SMPS_ASS_VDD2_EN2_MASK 0x04 539 #define EN2_SMPS_ASS_VDD2_EN2_SHIFT 2 540 #define EN2_SMPS_ASS_VDD1_EN2_MASK 0x02 541 #define EN2_SMPS_ASS_VDD1_EN2_SHIFT 1 542 #define EN2_SMPS_ASS_VIO_EN2_MASK 0x01 543 #define EN2_SMPS_ASS_VIO_EN2_SHIFT 0 544 545 546 /*Register EN3_LDO_ASS (0x80) register.RegisterDescription */ 547 #define EN3_LDO_ASS_VDAC_EN3_MASK 0x80 548 #define EN3_LDO_ASS_VDAC_EN3_SHIFT 7 549 #define EN3_LDO_ASS_VPLL_EN3_MASK 0x40 550 #define EN3_LDO_ASS_VPLL_EN3_SHIFT 6 551 #define EN3_LDO_ASS_VAUX33_EN3_MASK 0x20 552 #define EN3_LDO_ASS_VAUX33_EN3_SHIFT 5 553 #define EN3_LDO_ASS_VAUX2_EN3_MASK 0x10 554 #define EN3_LDO_ASS_VAUX2_EN3_SHIFT 4 555 #define EN3_LDO_ASS_VAUX1_EN3_MASK 0x08 556 #define EN3_LDO_ASS_VAUX1_EN3_SHIFT 3 557 #define EN3_LDO_ASS_VDIG2_EN3_MASK 0x04 558 #define EN3_LDO_ASS_VDIG2_EN3_SHIFT 2 559 #define EN3_LDO_ASS_VDIG1_EN3_MASK 0x02 560 #define EN3_LDO_ASS_VDIG1_EN3_SHIFT 1 561 #define EN3_LDO_ASS_VMMC_EN3_MASK 0x01 562 #define EN3_LDO_ASS_VMMC_EN3_SHIFT 0 563 564 565 /*Register SPARE (0x80) register.RegisterDescription */ 566 #define SPARE_SPARE_MASK 0xFF 567 #define SPARE_SPARE_SHIFT 0 568 569 #define TPS65910_INT_STS_RTC_PERIOD_IT_MASK 0x80 570 #define TPS65910_INT_STS_RTC_PERIOD_IT_SHIFT 7 571 #define TPS65910_INT_STS_RTC_ALARM_IT_MASK 0x40 572 #define TPS65910_INT_STS_RTC_ALARM_IT_SHIFT 6 573 #define TPS65910_INT_STS_HOTDIE_IT_MASK 0x20 574 #define TPS65910_INT_STS_HOTDIE_IT_SHIFT 5 575 #define TPS65910_INT_STS_PWRHOLD_F_IT_MASK 0x10 576 #define TPS65910_INT_STS_PWRHOLD_F_IT_SHIFT 4 577 #define TPS65910_INT_STS_PWRON_LP_IT_MASK 0x08 578 #define TPS65910_INT_STS_PWRON_LP_IT_SHIFT 3 579 #define TPS65910_INT_STS_PWRON_IT_MASK 0x04 580 #define TPS65910_INT_STS_PWRON_IT_SHIFT 2 581 #define TPS65910_INT_STS_VMBHI_IT_MASK 0x02 582 #define TPS65910_INT_STS_VMBHI_IT_SHIFT 1 583 #define TPS65910_INT_STS_VMBDCH_IT_MASK 0x01 584 #define TPS65910_INT_STS_VMBDCH_IT_SHIFT 0 585 586 #define TPS65910_INT_MSK_RTC_PERIOD_IT_MSK_MASK 0x80 587 #define TPS65910_INT_MSK_RTC_PERIOD_IT_MSK_SHIFT 7 588 #define TPS65910_INT_MSK_RTC_ALARM_IT_MSK_MASK 0x40 589 #define TPS65910_INT_MSK_RTC_ALARM_IT_MSK_SHIFT 6 590 #define TPS65910_INT_MSK_HOTDIE_IT_MSK_MASK 0x20 591 #define TPS65910_INT_MSK_HOTDIE_IT_MSK_SHIFT 5 592 #define TPS65910_INT_MSK_PWRHOLD_IT_MSK_MASK 0x10 593 #define TPS65910_INT_MSK_PWRHOLD_IT_MSK_SHIFT 4 594 #define TPS65910_INT_MSK_PWRON_LP_IT_MSK_MASK 0x08 595 #define TPS65910_INT_MSK_PWRON_LP_IT_MSK_SHIFT 3 596 #define TPS65910_INT_MSK_PWRON_IT_MSK_MASK 0x04 597 #define TPS65910_INT_MSK_PWRON_IT_MSK_SHIFT 2 598 #define TPS65910_INT_MSK_VMBHI_IT_MSK_MASK 0x02 599 #define TPS65910_INT_MSK_VMBHI_IT_MSK_SHIFT 1 600 #define TPS65910_INT_MSK_VMBDCH_IT_MSK_MASK 0x01 601 #define TPS65910_INT_MSK_VMBDCH_IT_MSK_SHIFT 0 602 603 #define TPS65910_INT_STS2_GPIO0_F_IT_SHIFT 2 604 #define TPS65910_INT_STS2_GPIO0_F_IT_MASK 0x02 605 #define TPS65910_INT_STS2_GPIO0_R_IT_SHIFT 1 606 #define TPS65910_INT_STS2_GPIO0_R_IT_MASK 0x01 607 608 #define TPS65910_INT_MSK2_GPIO0_F_IT_MSK_SHIFT 2 609 #define TPS65910_INT_MSK2_GPIO0_F_IT_MSK_MASK 0x02 610 #define TPS65910_INT_MSK2_GPIO0_R_IT_MSK_SHIFT 1 611 #define TPS65910_INT_MSK2_GPIO0_R_IT_MSK_MASK 0x01 612 613 /*Register INT_STS (0x80) register.RegisterDescription */ 614 #define INT_STS_RTC_PERIOD_IT_MASK 0x80 615 #define INT_STS_RTC_PERIOD_IT_SHIFT 7 616 #define INT_STS_RTC_ALARM_IT_MASK 0x40 617 #define INT_STS_RTC_ALARM_IT_SHIFT 6 618 #define INT_STS_HOTDIE_IT_MASK 0x20 619 #define INT_STS_HOTDIE_IT_SHIFT 5 620 #define INT_STS_PWRHOLD_R_IT_MASK 0x10 621 #define INT_STS_PWRHOLD_R_IT_SHIFT 4 622 #define INT_STS_PWRON_LP_IT_MASK 0x08 623 #define INT_STS_PWRON_LP_IT_SHIFT 3 624 #define INT_STS_PWRON_IT_MASK 0x04 625 #define INT_STS_PWRON_IT_SHIFT 2 626 #define INT_STS_VMBHI_IT_MASK 0x02 627 #define INT_STS_VMBHI_IT_SHIFT 1 628 #define INT_STS_PWRHOLD_F_IT_MASK 0x01 629 #define INT_STS_PWRHOLD_F_IT_SHIFT 0 630 631 632 /*Register INT_MSK (0x80) register.RegisterDescription */ 633 #define INT_MSK_RTC_PERIOD_IT_MSK_MASK 0x80 634 #define INT_MSK_RTC_PERIOD_IT_MSK_SHIFT 7 635 #define INT_MSK_RTC_ALARM_IT_MSK_MASK 0x40 636 #define INT_MSK_RTC_ALARM_IT_MSK_SHIFT 6 637 #define INT_MSK_HOTDIE_IT_MSK_MASK 0x20 638 #define INT_MSK_HOTDIE_IT_MSK_SHIFT 5 639 #define INT_MSK_PWRHOLD_R_IT_MSK_MASK 0x10 640 #define INT_MSK_PWRHOLD_R_IT_MSK_SHIFT 4 641 #define INT_MSK_PWRON_LP_IT_MSK_MASK 0x08 642 #define INT_MSK_PWRON_LP_IT_MSK_SHIFT 3 643 #define INT_MSK_PWRON_IT_MSK_MASK 0x04 644 #define INT_MSK_PWRON_IT_MSK_SHIFT 2 645 #define INT_MSK_VMBHI_IT_MSK_MASK 0x02 646 #define INT_MSK_VMBHI_IT_MSK_SHIFT 1 647 #define INT_MSK_PWRHOLD_F_IT_MSK_MASK 0x01 648 #define INT_MSK_PWRHOLD_F_IT_MSK_SHIFT 0 649 650 651 /*Register INT_STS2 (0x80) register.RegisterDescription */ 652 #define INT_STS2_GPIO3_F_IT_MASK 0x80 653 #define INT_STS2_GPIO3_F_IT_SHIFT 7 654 #define INT_STS2_GPIO3_R_IT_MASK 0x40 655 #define INT_STS2_GPIO3_R_IT_SHIFT 6 656 #define INT_STS2_GPIO2_F_IT_MASK 0x20 657 #define INT_STS2_GPIO2_F_IT_SHIFT 5 658 #define INT_STS2_GPIO2_R_IT_MASK 0x10 659 #define INT_STS2_GPIO2_R_IT_SHIFT 4 660 #define INT_STS2_GPIO1_F_IT_MASK 0x08 661 #define INT_STS2_GPIO1_F_IT_SHIFT 3 662 #define INT_STS2_GPIO1_R_IT_MASK 0x04 663 #define INT_STS2_GPIO1_R_IT_SHIFT 2 664 #define INT_STS2_GPIO0_F_IT_MASK 0x02 665 #define INT_STS2_GPIO0_F_IT_SHIFT 1 666 #define INT_STS2_GPIO0_R_IT_MASK 0x01 667 #define INT_STS2_GPIO0_R_IT_SHIFT 0 668 669 670 /*Register INT_MSK2 (0x80) register.RegisterDescription */ 671 #define INT_MSK2_GPIO3_F_IT_MSK_MASK 0x80 672 #define INT_MSK2_GPIO3_F_IT_MSK_SHIFT 7 673 #define INT_MSK2_GPIO3_R_IT_MSK_MASK 0x40 674 #define INT_MSK2_GPIO3_R_IT_MSK_SHIFT 6 675 #define INT_MSK2_GPIO2_F_IT_MSK_MASK 0x20 676 #define INT_MSK2_GPIO2_F_IT_MSK_SHIFT 5 677 #define INT_MSK2_GPIO2_R_IT_MSK_MASK 0x10 678 #define INT_MSK2_GPIO2_R_IT_MSK_SHIFT 4 679 #define INT_MSK2_GPIO1_F_IT_MSK_MASK 0x08 680 #define INT_MSK2_GPIO1_F_IT_MSK_SHIFT 3 681 #define INT_MSK2_GPIO1_R_IT_MSK_MASK 0x04 682 #define INT_MSK2_GPIO1_R_IT_MSK_SHIFT 2 683 #define INT_MSK2_GPIO0_F_IT_MSK_MASK 0x02 684 #define INT_MSK2_GPIO0_F_IT_MSK_SHIFT 1 685 #define INT_MSK2_GPIO0_R_IT_MSK_MASK 0x01 686 #define INT_MSK2_GPIO0_R_IT_MSK_SHIFT 0 687 688 689 /*Register INT_STS3 (0x80) register.RegisterDescription */ 690 #define INT_STS3_PWRDN_IT_MASK 0x80 691 #define INT_STS3_PWRDN_IT_SHIFT 7 692 #define INT_STS3_VMBCH2_L_IT_MASK 0x40 693 #define INT_STS3_VMBCH2_L_IT_SHIFT 6 694 #define INT_STS3_VMBCH2_H_IT_MASK 0x20 695 #define INT_STS3_VMBCH2_H_IT_SHIFT 5 696 #define INT_STS3_WTCHDG_IT_MASK 0x10 697 #define INT_STS3_WTCHDG_IT_SHIFT 4 698 #define INT_STS3_GPIO5_F_IT_MASK 0x08 699 #define INT_STS3_GPIO5_F_IT_SHIFT 3 700 #define INT_STS3_GPIO5_R_IT_MASK 0x04 701 #define INT_STS3_GPIO5_R_IT_SHIFT 2 702 #define INT_STS3_GPIO4_F_IT_MASK 0x02 703 #define INT_STS3_GPIO4_F_IT_SHIFT 1 704 #define INT_STS3_GPIO4_R_IT_MASK 0x01 705 #define INT_STS3_GPIO4_R_IT_SHIFT 0 706 707 708 /*Register INT_MSK3 (0x80) register.RegisterDescription */ 709 #define INT_MSK3_PWRDN_IT_MSK_MASK 0x80 710 #define INT_MSK3_PWRDN_IT_MSK_SHIFT 7 711 #define INT_MSK3_VMBCH2_L_IT_MSK_MASK 0x40 712 #define INT_MSK3_VMBCH2_L_IT_MSK_SHIFT 6 713 #define INT_MSK3_VMBCH2_H_IT_MSK_MASK 0x20 714 #define INT_MSK3_VMBCH2_H_IT_MSK_SHIFT 5 715 #define INT_MSK3_WTCHDG_IT_MSK_MASK 0x10 716 #define INT_MSK3_WTCHDG_IT_MSK_SHIFT 4 717 #define INT_MSK3_GPIO5_F_IT_MSK_MASK 0x08 718 #define INT_MSK3_GPIO5_F_IT_MSK_SHIFT 3 719 #define INT_MSK3_GPIO5_R_IT_MSK_MASK 0x04 720 #define INT_MSK3_GPIO5_R_IT_MSK_SHIFT 2 721 #define INT_MSK3_GPIO4_F_IT_MSK_MASK 0x02 722 #define INT_MSK3_GPIO4_F_IT_MSK_SHIFT 1 723 #define INT_MSK3_GPIO4_R_IT_MSK_MASK 0x01 724 #define INT_MSK3_GPIO4_R_IT_MSK_SHIFT 0 725 726 727 /*Register GPIO (0x80) register.RegisterDescription */ 728 #define GPIO_SLEEP_MASK 0x80 729 #define GPIO_SLEEP_SHIFT 7 730 #define GPIO_DEB_MASK 0x10 731 #define GPIO_DEB_SHIFT 4 732 #define GPIO_PUEN_MASK 0x08 733 #define GPIO_PUEN_SHIFT 3 734 #define GPIO_CFG_MASK 0x04 735 #define GPIO_CFG_SHIFT 2 736 #define GPIO_STS_MASK 0x02 737 #define GPIO_STS_SHIFT 1 738 #define GPIO_SET_MASK 0x01 739 #define GPIO_SET_SHIFT 0 740 741 742 /*Register JTAGVERNUM (0x80) register.RegisterDescription */ 743 #define JTAGVERNUM_VERNUM_MASK 0x0F 744 #define JTAGVERNUM_VERNUM_SHIFT 0 745 746 747 /* Register VDDCTRL (0x27) bit definitions */ 748 #define VDDCTRL_ST_MASK 0x03 749 #define VDDCTRL_ST_SHIFT 0 750 751 752 /*Register VDDCTRL_OP (0x28) bit definitions */ 753 #define VDDCTRL_OP_CMD_MASK 0x80 754 #define VDDCTRL_OP_CMD_SHIFT 7 755 #define VDDCTRL_OP_SEL_MASK 0x7F 756 #define VDDCTRL_OP_SEL_SHIFT 0 757 758 759 /*Register VDDCTRL_SR (0x29) bit definitions */ 760 #define VDDCTRL_SR_SEL_MASK 0x7F 761 #define VDDCTRL_SR_SEL_SHIFT 0 762 763 764 /* IRQ Definitions */ 765 #define TPS65910_IRQ_VBAT_VMBDCH 0 766 #define TPS65910_IRQ_VBAT_VMHI 1 767 #define TPS65910_IRQ_PWRON 2 768 #define TPS65910_IRQ_PWRON_LP 3 769 #define TPS65910_IRQ_PWRHOLD 4 770 #define TPS65910_IRQ_HOTDIE 5 771 #define TPS65910_IRQ_RTC_ALARM 6 772 #define TPS65910_IRQ_RTC_PERIOD 7 773 #define TPS65910_IRQ_GPIO_R 8 774 #define TPS65910_IRQ_GPIO_F 9 775 #define TPS65910_NUM_IRQ 10 776 777 #define TPS65911_IRQ_PWRHOLD_F 0 778 #define TPS65911_IRQ_VBAT_VMHI 1 779 #define TPS65911_IRQ_PWRON 2 780 #define TPS65911_IRQ_PWRON_LP 3 781 #define TPS65911_IRQ_PWRHOLD_R 4 782 #define TPS65911_IRQ_HOTDIE 5 783 #define TPS65911_IRQ_RTC_ALARM 6 784 #define TPS65911_IRQ_RTC_PERIOD 7 785 #define TPS65911_IRQ_GPIO0_R 8 786 #define TPS65911_IRQ_GPIO0_F 9 787 #define TPS65911_IRQ_GPIO1_R 10 788 #define TPS65911_IRQ_GPIO1_F 11 789 #define TPS65911_IRQ_GPIO2_R 12 790 #define TPS65911_IRQ_GPIO2_F 13 791 #define TPS65911_IRQ_GPIO3_R 14 792 #define TPS65911_IRQ_GPIO3_F 15 793 #define TPS65911_IRQ_GPIO4_R 16 794 #define TPS65911_IRQ_GPIO4_F 17 795 #define TPS65911_IRQ_GPIO5_R 18 796 #define TPS65911_IRQ_GPIO5_F 19 797 #define TPS65911_IRQ_WTCHDG 20 798 #define TPS65911_IRQ_VMBCH2_H 21 799 #define TPS65911_IRQ_VMBCH2_L 22 800 #define TPS65911_IRQ_PWRDN 23 801 802 #define TPS65911_NUM_IRQ 24 803 804 /* GPIO Register Definitions */ 805 #define TPS65910_GPIO_DEB BIT(2) 806 #define TPS65910_GPIO_PUEN BIT(3) 807 #define TPS65910_GPIO_CFG BIT(2) 808 #define TPS65910_GPIO_STS BIT(1) 809 #define TPS65910_GPIO_SET BIT(0) 810 811 /* Max number of TPS65910/11 GPIOs */ 812 #define TPS65910_NUM_GPIO 6 813 #define TPS65911_NUM_GPIO 9 814 #define TPS6591X_MAX_NUM_GPIO 9 815 816 /* Regulator Index Definitions */ 817 #define TPS65910_REG_VRTC 0 818 #define TPS65910_REG_VIO 1 819 #define TPS65910_REG_VDD1 2 820 #define TPS65910_REG_VDD2 3 821 #define TPS65910_REG_VDD3 4 822 #define TPS65910_REG_VDIG1 5 823 #define TPS65910_REG_VDIG2 6 824 #define TPS65910_REG_VPLL 7 825 #define TPS65910_REG_VDAC 8 826 #define TPS65910_REG_VAUX1 9 827 #define TPS65910_REG_VAUX2 10 828 #define TPS65910_REG_VAUX33 11 829 #define TPS65910_REG_VMMC 12 830 #define TPS65910_REG_VBB 13 831 832 #define TPS65911_REG_VDDCTRL 4 833 #define TPS65911_REG_LDO1 5 834 #define TPS65911_REG_LDO2 6 835 #define TPS65911_REG_LDO3 7 836 #define TPS65911_REG_LDO4 8 837 #define TPS65911_REG_LDO5 9 838 #define TPS65911_REG_LDO6 10 839 #define TPS65911_REG_LDO7 11 840 #define TPS65911_REG_LDO8 12 841 842 /* Max number of TPS65910/11 regulators */ 843 #define TPS65910_NUM_REGS 14 844 845 /* External sleep controls through EN1/EN2/EN3/SLEEP inputs */ 846 #define TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1 0x1 847 #define TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2 0x2 848 #define TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3 0x4 849 #define TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP 0x8 850 851 /* 852 * Sleep keepon data: Maintains the state in sleep mode 853 * @therm_keepon: Keep on the thermal monitoring in sleep state. 854 * @clkout32k_keepon: Keep on the 32KHz clock output in sleep state. 855 * @i2chs_keepon: Keep on high speed internal clock in sleep state. 856 */ 857 struct tps65910_sleep_keepon_data { 858 unsigned therm_keepon:1; 859 unsigned clkout32k_keepon:1; 860 unsigned i2chs_keepon:1; 861 }; 862 863 /** 864 * struct tps65910_board 865 * Board platform data may be used to initialize regulators. 866 */ 867 868 struct tps65910_board { 869 int gpio_base; 870 int irq; 871 int irq_base; 872 int vmbch_threshold; 873 int vmbch2_threshold; 874 bool en_ck32k_xtal; 875 bool en_dev_slp; 876 bool pm_off; 877 struct tps65910_sleep_keepon_data slp_keepon; 878 bool en_gpio_sleep[TPS6591X_MAX_NUM_GPIO]; 879 unsigned long regulator_ext_sleep_control[TPS65910_NUM_REGS]; 880 struct regulator_init_data *tps65910_pmic_init_data[TPS65910_NUM_REGS]; 881 }; 882 883 /** 884 * struct tps65910 - tps65910 sub-driver chip access routines 885 */ 886 887 struct tps65910 { 888 struct device *dev; 889 struct i2c_client *i2c_client; 890 struct regmap *regmap; 891 unsigned long id; 892 893 /* Device node parsed board data */ 894 struct tps65910_board *of_plat_data; 895 896 /* IRQ Handling */ 897 int chip_irq; 898 struct regmap_irq_chip_data *irq_data; 899 }; 900 901 struct tps65910_platform_data { 902 int irq; 903 int irq_base; 904 }; 905 tps65910_chip_id(struct tps65910 * tps65910)906 static inline int tps65910_chip_id(struct tps65910 *tps65910) 907 { 908 return tps65910->id; 909 } 910 911 #endif /* __LINUX_MFD_TPS65910_H */ 912