Searched refs:DDI_CLK_SEL_MASK (Results 1 – 2 of 2) sorted by relevance
3999 #define DDI_CLK_SEL_MASK REG_GENMASK(31, 28) macro4000 #define DDI_CLK_SEL_NONE REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x0)4001 #define DDI_CLK_SEL_MG REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x8)4002 #define DDI_CLK_SEL_TBT_162 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xC)4003 #define DDI_CLK_SEL_TBT_270 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xD)4004 #define DDI_CLK_SEL_TBT_540 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xE)4005 #define DDI_CLK_SEL_TBT_810 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xF)
358 u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; in icl_calc_tbt_pll_link()1765 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) in jsl_ddi_tc_is_clock_enabled()1818 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) in icl_ddi_tc_is_clock_enabled()1836 switch (tmp & DDI_CLK_SEL_MASK) { in icl_ddi_tc_get_pll()