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Searched refs:DC__VOLTAGE_STATES (Results 1 – 13 of 13) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/
Ddisplay_mode_vba.h317 …double ActiveDRAMClockChangeLatencyMarginPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];// DML …
536 unsigned int PrefetchMode[DC__VOLTAGE_STATES][2];
537 unsigned int PrefetchModePerState[DC__VOLTAGE_STATES][2];
599 double DCFCLKPerState[DC__VOLTAGE_STATES];
600 double DCFCLKState[DC__VOLTAGE_STATES][2];
601 double FabricClockPerState[DC__VOLTAGE_STATES];
602 double SOCCLKPerState[DC__VOLTAGE_STATES];
603 double PHYCLKPerState[DC__VOLTAGE_STATES];
604 double DTBCLKPerState[DC__VOLTAGE_STATES];
605 double MaxDppclk[DC__VOLTAGE_STATES];
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Ddc_features.h39 #define DC__VOLTAGE_STATES 40 macro
Ddisplay_mode_structs.h182 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn302/
Ddcn302_fpu.c200 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; in dcn302_fpu_update_bw_bounding_box()
201 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; in dcn302_fpu_update_bw_bounding_box()
202 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; in dcn302_fpu_update_bw_bounding_box()
203 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; in dcn302_fpu_update_bw_bounding_box()
205 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200}; in dcn302_fpu_update_bw_bounding_box()
282 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn302_fpu_update_bw_bounding_box()
296 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn302_fpu_update_bw_bounding_box()
301 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn302_fpu_update_bw_bounding_box()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn303/
Ddcn303_fpu.c196 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; in dcn303_fpu_update_bw_bounding_box()
197 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; in dcn303_fpu_update_bw_bounding_box()
198 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; in dcn303_fpu_update_bw_bounding_box()
199 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; in dcn303_fpu_update_bw_bounding_box()
201 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200}; in dcn303_fpu_update_bw_bounding_box()
287 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn303_fpu_update_bw_bounding_box()
302 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn303_fpu_update_bw_bounding_box()
307 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn303_fpu_update_bw_bounding_box()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn321/
Ddcn321_fpu.c354 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564}; in build_synthetic_soc_states()
712 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; in dcn321_update_bw_bounding_box_fpu()
713 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; in dcn321_update_bw_bounding_box_fpu()
714 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; in dcn321_update_bw_bounding_box_fpu()
715 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; in dcn321_update_bw_bounding_box_fpu()
717 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {615, 906, 1324, 1564}; in dcn321_update_bw_bounding_box_fpu()
781 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn321_update_bw_bounding_box_fpu()
795 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn321_update_bw_bounding_box_fpu()
800 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn321_update_bw_bounding_box_fpu()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn30/
Ddcn30_resource.c2105 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; in dcn30_update_bw_bounding_box()
2106 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; in dcn30_update_bw_bounding_box()
2107 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; in dcn30_update_bw_bounding_box()
2108 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; in dcn30_update_bw_bounding_box()
2110 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200}; in dcn30_update_bw_bounding_box()
2196 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn30_update_bw_bounding_box()
2210 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn30_update_bw_bounding_box()
2215 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn30_update_bw_bounding_box()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn32/
Ddcn32_fpu.c2806 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564}; in build_synthetic_soc_states()
3149 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; in dcn32_update_bw_bounding_box_fpu()
3150 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; in dcn32_update_bw_bounding_box_fpu()
3151 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; in dcn32_update_bw_bounding_box_fpu()
3152 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; in dcn32_update_bw_bounding_box_fpu()
3156 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564}; in dcn32_update_bw_bounding_box_fpu()
3225 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn32_update_bw_bounding_box_fpu()
3239 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn32_update_bw_bounding_box_fpu()
3244 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn32_update_bw_bounding_box_fpu()
Ddisplay_mode_vba_util_32.c2980 double TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2]; in dml32_UseMinimumDCFCLK()
2983 for (i = 0; i < DC__VOLTAGE_STATES; ++i) { in dml32_UseMinimumDCFCLK()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/
Ddc.h1459 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn30/
Ddisplay_mode_vba_30.c6507 double TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2] = { { 0 } }; in UseMinimumDCFCLK()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn31/
Ddisplay_mode_vba_31.c7035 double TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2];
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn314/
Ddisplay_mode_vba_314.c7122 double TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2];