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Searched refs:DCN_BASE__INST0_SEG4 (Results 1 – 16 of 16) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/display/dmub/src/
Ddmub_dcn315.c37 #define DCN_BASE__INST0_SEG4 0x02403C00 macro
Ddmub_dcn316.c37 #define DCN_BASE__INST0_SEG4 0x02403C00 macro
Ddmub_dcn314.c37 #define DCN_BASE__INST0_SEG4 0x02403C00 macro
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/gpio/dcn315/
Dhw_factory_dcn315.c49 #define DCN_BASE__INST0_SEG4 0x02403C00 macro
Dhw_translate_dcn315.c42 #define DCN_BASE__INST0_SEG4 0x02403C00 macro
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/irq/dcn315/
Dirq_service_dcn315.c42 #define DCN_BASE__INST0_SEG4 0x02403C00 macro
/linux-6.12.1/drivers/gpu/drm/amd/include/
Dnavi10_ip_offset.h271 #define DCN_BASE__INST0_SEG4 0 macro
Ddimgrey_cavefish_ip_offset.h365 #define DCN_BASE__INST0_SEG4 0x02403C00 macro
Dsienna_cichlid_ip_offset.h372 #define DCN_BASE__INST0_SEG4 0x02403C00 macro
Dbeige_goby_ip_offset.h443 #define DCN_BASE__INST0_SEG4 0x02403C00 macro
Drenoir_ip_offset.h1371 #define DCN_BASE__INST0_SEG4 0 macro
Dvega10_ip_offset.h307 #define DCN_BASE__INST0_SEG4 0 macro
Dvangogh_ip_offset.h454 #define DCN_BASE__INST0_SEG4 0x02403C00 macro
Dyellow_carp_offset.h389 #define DCN_BASE__INST0_SEG4 0x02403C00 macro
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn316/
Ddcn316_resource.c98 #define DCN_BASE__INST0_SEG4 0x02403C00 macro
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn315/
Ddcn315_resource.c100 #define DCN_BASE__INST0_SEG4 0x02403C00 macro