Home
last modified time | relevance | path

Searched refs:DCN_BASE__INST0_SEG0 (Results 1 – 16 of 16) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/display/dmub/src/
Ddmub_dcn315.c33 #define DCN_BASE__INST0_SEG0 0x00000012 macro
Ddmub_dcn316.c33 #define DCN_BASE__INST0_SEG0 0x00000012 macro
Ddmub_dcn314.c33 #define DCN_BASE__INST0_SEG0 0x00000012 macro
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/gpio/dcn315/
Dhw_factory_dcn315.c45 #define DCN_BASE__INST0_SEG0 0x00000012 macro
Dhw_translate_dcn315.c38 #define DCN_BASE__INST0_SEG0 0x00000012 macro
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/irq/dcn315/
Dirq_service_dcn315.c38 #define DCN_BASE__INST0_SEG0 0x00000012 macro
/linux-6.12.1/drivers/gpu/drm/amd/include/
Dnavi10_ip_offset.h267 #define DCN_BASE__INST0_SEG0 0x00000012 macro
Ddimgrey_cavefish_ip_offset.h361 #define DCN_BASE__INST0_SEG0 0x00000012 macro
Dsienna_cichlid_ip_offset.h368 #define DCN_BASE__INST0_SEG0 0x00000012 macro
Dbeige_goby_ip_offset.h439 #define DCN_BASE__INST0_SEG0 0x00000012 macro
Drenoir_ip_offset.h1367 #define DCN_BASE__INST0_SEG0 0x00000012 macro
Dvega10_ip_offset.h303 #define DCN_BASE__INST0_SEG0 0x00000012 macro
Dvangogh_ip_offset.h450 #define DCN_BASE__INST0_SEG0 0x00000012 macro
Dyellow_carp_offset.h385 #define DCN_BASE__INST0_SEG0 0x00000012 macro
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn316/
Ddcn316_resource.c94 #define DCN_BASE__INST0_SEG0 0x00000012 macro
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn315/
Ddcn315_resource.c96 #define DCN_BASE__INST0_SEG0 0x00000012 macro