Searched refs:DCLK_VOP0_DIV (Results 1 – 3 of 3) sorted by relevance
672 assigned-clocks = <&cru DCLK_VOP0_DIV>, <&cru DCLK_VOP0>,675 assigned-clock-parents = <&cru PLL_GPLL>, <&cru DCLK_VOP0_DIV>;
131 #define DCLK_VOP0_DIV 182 macro
1165 COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, 0,