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Searched refs:DCCG_GATE_DISABLE_CNTL3 (Results 1 – 9 of 9) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dccg/dcn401/
Ddcn401_dccg.h129 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, HDMISTREAMCLK0_GATE_DISABLE, mask_sh),\
130 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE0_GATE_DISABLE, mask_sh),\
131 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE1_GATE_DISABLE, mask_sh),\
132 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE2_GATE_DISABLE, mask_sh),\
133 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE3_GATE_DISABLE, mask_sh),\
134 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE0_GATE_DISABLE, mask_sh),\
135 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE1_GATE_DISABLE, mask_sh),\
136 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE2_GATE_DISABLE, mask_sh),\
137 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE3_GATE_DISABLE, mask_sh),\
138 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE0_GATE_DISABLE, mask_sh),\
[all …]
Ddcn401_dccg.c392 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, in dccg401_enable_symclk32_le()
401 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, in dccg401_enable_symclk32_le()
410 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, in dccg401_enable_symclk32_le()
419 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, in dccg401_enable_symclk32_le()
445 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, in dccg401_disable_symclk32_le()
454 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, in dccg401_disable_symclk32_le()
463 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, in dccg401_disable_symclk32_le()
472 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, in dccg401_disable_symclk32_le()
529 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, in dccg401_enable_dpstreamclk()
634 REG_UPDATE_4(DCCG_GATE_DISABLE_CNTL3, in dccg401_set_dp_dto()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dccg/dcn314/
Ddcn314_dccg.h74 SR(DCCG_GATE_DISABLE_CNTL3),\
155 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE0_GATE_DISABLE, mask_sh),\
156 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE1_GATE_DISABLE, mask_sh),\
157 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE2_GATE_DISABLE, mask_sh),\
158 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE3_GATE_DISABLE, mask_sh),\
159 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE0_GATE_DISABLE, mask_sh),\
160 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE1_GATE_DISABLE, mask_sh),\
161 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE0_GATE_DISABLE, mask_sh),\
162 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE1_GATE_DISABLE, mask_sh),\
163 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE2_GATE_DISABLE, mask_sh),\
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dccg/dcn35/
Ddcn35_dccg.h205 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE0_GATE_DISABLE, mask_sh),\
206 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE1_GATE_DISABLE, mask_sh),\
207 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE2_GATE_DISABLE, mask_sh),\
208 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE3_GATE_DISABLE, mask_sh),\
209 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE0_GATE_DISABLE, mask_sh),\
210 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE1_GATE_DISABLE, mask_sh),\
211 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE0_GATE_DISABLE, mask_sh),\
212 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE1_GATE_DISABLE, mask_sh),\
213 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE2_GATE_DISABLE, mask_sh),\
214 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE3_GATE_DISABLE, mask_sh),\
[all …]
Ddcn35_dccg.c176 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, in dccg35_set_symclk32_se_rcg()
181 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, in dccg35_set_symclk32_se_rcg()
186 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, in dccg35_set_symclk32_se_rcg()
191 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, in dccg35_set_symclk32_se_rcg()
213 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, in dccg35_set_symclk32_le_rcg()
218 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, in dccg35_set_symclk32_le_rcg()
465 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, in dccg35_set_smclk32_se_rcg()
470 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, in dccg35_set_smclk32_se_rcg()
475 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, in dccg35_set_smclk32_se_rcg()
480 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, in dccg35_set_smclk32_se_rcg()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dccg/dcn31/
Ddcn31_dccg.h68 SR(DCCG_GATE_DISABLE_CNTL3),\
150 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, DPSTREAMCLK_ROOT_GATE_DISABLE, mask_sh),\
151 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, DPSTREAMCLK_GATE_DISABLE, mask_sh),\
152 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE0_GATE_DISABLE, mask_sh),\
153 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE1_GATE_DISABLE, mask_sh),\
154 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE2_GATE_DISABLE, mask_sh),\
155 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE3_GATE_DISABLE, mask_sh),\
156 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE0_GATE_DISABLE, mask_sh),\
157 DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE1_GATE_DISABLE, mask_sh),\
Ddcn31_dccg.c124 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, in dccg31_enable_dpstreamclk()
134 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, in dccg31_disable_dpstreamclk()
186 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, in dccg31_enable_symclk32_se()
195 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, in dccg31_enable_symclk32_se()
204 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, in dccg31_enable_symclk32_se()
213 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, in dccg31_enable_symclk32_se()
239 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, in dccg31_disable_symclk32_se()
248 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, in dccg31_disable_symclk32_se()
257 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, in dccg31_disable_symclk32_se()
266 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, in dccg31_disable_symclk32_se()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dccg/dcn20/
Ddcn20_dccg.h413 uint32_t DCCG_GATE_DISABLE_CNTL3; member
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn401/
Ddcn401_resource.h640 SR(DCCG_GATE_DISABLE_CNTL3),\