Searched refs:CSI2_RX_CFG0_DL0_INPUT_SEL (Results 1 – 1 of 1) sorted by relevance
57 #define CSI2_RX_CFG0_DL0_INPUT_SEL 4 macro189 val |= phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL; in __csid_configure_rx()