1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* ZD1211 USB-WLAN driver for Linux 3 * 4 * Copyright (C) 2005-2007 Ulrich Kunitz <kune@deine-taler.de> 5 * Copyright (C) 2006-2007 Daniel Drake <dsd@gentoo.org> 6 */ 7 8 #ifndef _ZD_CHIP_H 9 #define _ZD_CHIP_H 10 11 #include <net/mac80211.h> 12 13 #include "zd_rf.h" 14 #include "zd_usb.h" 15 16 /* Header for the Media Access Controller (MAC) and the Baseband Processor 17 * (BBP). It appears that the ZD1211 wraps the old ZD1205 with USB glue and 18 * adds a processor for handling the USB protocol. 19 */ 20 21 /* Address space */ 22 enum { 23 /* CONTROL REGISTERS */ 24 CR_START = 0x9000, 25 26 27 /* FIRMWARE */ 28 FW_START = 0xee00, 29 30 31 /* EEPROM */ 32 E2P_START = 0xf800, 33 E2P_LEN = 0x800, 34 35 /* EEPROM layout */ 36 E2P_LOAD_CODE_LEN = 0xe, /* base 0xf800 */ 37 E2P_LOAD_VECT_LEN = 0x9, /* base 0xf80e */ 38 /* E2P_DATA indexes into this */ 39 E2P_DATA_LEN = 0x7e, /* base 0xf817 */ 40 E2P_BOOT_CODE_LEN = 0x760, /* base 0xf895 */ 41 E2P_INTR_VECT_LEN = 0xb, /* base 0xfff5 */ 42 43 /* Some precomputed offsets into the EEPROM */ 44 E2P_DATA_OFFSET = E2P_LOAD_CODE_LEN + E2P_LOAD_VECT_LEN, 45 E2P_BOOT_CODE_OFFSET = E2P_DATA_OFFSET + E2P_DATA_LEN, 46 }; 47 48 #define CTL_REG(offset) ((zd_addr_t)(CR_START + (offset))) 49 #define E2P_DATA(offset) ((zd_addr_t)(E2P_START + E2P_DATA_OFFSET + (offset))) 50 #define FWRAW_DATA(offset) ((zd_addr_t)(FW_START + (offset))) 51 52 /* 8-bit hardware registers */ 53 #define ZD_CR0 CTL_REG(0x0000) 54 #define ZD_CR1 CTL_REG(0x0004) 55 #define ZD_CR2 CTL_REG(0x0008) 56 #define ZD_CR3 CTL_REG(0x000C) 57 58 #define ZD_CR5 CTL_REG(0x0010) 59 /* bit 5: if set short preamble used 60 * bit 6: filter band - Japan channel 14 on, else off 61 */ 62 #define ZD_CR6 CTL_REG(0x0014) 63 #define ZD_CR7 CTL_REG(0x0018) 64 #define ZD_CR8 CTL_REG(0x001C) 65 66 #define ZD_CR4 CTL_REG(0x0020) 67 68 #define ZD_CR9 CTL_REG(0x0024) 69 /* bit 2: antenna switch (together with ZD_CR10) */ 70 #define ZD_CR10 CTL_REG(0x0028) 71 /* bit 1: antenna switch (together with ZD_CR9) 72 * RF2959 controls with ZD_CR11 radion on and off 73 */ 74 #define ZD_CR11 CTL_REG(0x002C) 75 /* bit 6: TX power control for OFDM 76 * RF2959 controls with ZD_CR10 radio on and off 77 */ 78 #define ZD_CR12 CTL_REG(0x0030) 79 #define ZD_CR13 CTL_REG(0x0034) 80 #define ZD_CR14 CTL_REG(0x0038) 81 #define ZD_CR15 CTL_REG(0x003C) 82 #define ZD_CR16 CTL_REG(0x0040) 83 #define ZD_CR17 CTL_REG(0x0044) 84 #define ZD_CR18 CTL_REG(0x0048) 85 #define ZD_CR19 CTL_REG(0x004C) 86 #define ZD_CR20 CTL_REG(0x0050) 87 #define ZD_CR21 CTL_REG(0x0054) 88 #define ZD_CR22 CTL_REG(0x0058) 89 #define ZD_CR23 CTL_REG(0x005C) 90 #define ZD_CR24 CTL_REG(0x0060) /* CCA threshold */ 91 #define ZD_CR25 CTL_REG(0x0064) 92 #define ZD_CR26 CTL_REG(0x0068) 93 #define ZD_CR27 CTL_REG(0x006C) 94 #define ZD_CR28 CTL_REG(0x0070) 95 #define ZD_CR29 CTL_REG(0x0074) 96 #define ZD_CR30 CTL_REG(0x0078) 97 #define ZD_CR31 CTL_REG(0x007C) /* TX power control for RF in 98 * CCK mode 99 */ 100 #define ZD_CR32 CTL_REG(0x0080) 101 #define ZD_CR33 CTL_REG(0x0084) 102 #define ZD_CR34 CTL_REG(0x0088) 103 #define ZD_CR35 CTL_REG(0x008C) 104 #define ZD_CR36 CTL_REG(0x0090) 105 #define ZD_CR37 CTL_REG(0x0094) 106 #define ZD_CR38 CTL_REG(0x0098) 107 #define ZD_CR39 CTL_REG(0x009C) 108 #define ZD_CR40 CTL_REG(0x00A0) 109 #define ZD_CR41 CTL_REG(0x00A4) 110 #define ZD_CR42 CTL_REG(0x00A8) 111 #define ZD_CR43 CTL_REG(0x00AC) 112 #define ZD_CR44 CTL_REG(0x00B0) 113 #define ZD_CR45 CTL_REG(0x00B4) 114 #define ZD_CR46 CTL_REG(0x00B8) 115 #define ZD_CR47 CTL_REG(0x00BC) /* CCK baseband gain 116 * (patch value might be in EEPROM) 117 */ 118 #define ZD_CR48 CTL_REG(0x00C0) 119 #define ZD_CR49 CTL_REG(0x00C4) 120 #define ZD_CR50 CTL_REG(0x00C8) 121 #define ZD_CR51 CTL_REG(0x00CC) /* TX power control for RF in 122 * 6-36M modes 123 */ 124 #define ZD_CR52 CTL_REG(0x00D0) /* TX power control for RF in 125 * 48M mode 126 */ 127 #define ZD_CR53 CTL_REG(0x00D4) /* TX power control for RF in 128 * 54M mode 129 */ 130 #define ZD_CR54 CTL_REG(0x00D8) 131 #define ZD_CR55 CTL_REG(0x00DC) 132 #define ZD_CR56 CTL_REG(0x00E0) 133 #define ZD_CR57 CTL_REG(0x00E4) 134 #define ZD_CR58 CTL_REG(0x00E8) 135 #define ZD_CR59 CTL_REG(0x00EC) 136 #define ZD_CR60 CTL_REG(0x00F0) 137 #define ZD_CR61 CTL_REG(0x00F4) 138 #define ZD_CR62 CTL_REG(0x00F8) 139 #define ZD_CR63 CTL_REG(0x00FC) 140 #define ZD_CR64 CTL_REG(0x0100) 141 #define ZD_CR65 CTL_REG(0x0104) /* OFDM 54M calibration */ 142 #define ZD_CR66 CTL_REG(0x0108) /* OFDM 48M calibration */ 143 #define ZD_CR67 CTL_REG(0x010C) /* OFDM 36M calibration */ 144 #define ZD_CR68 CTL_REG(0x0110) /* CCK calibration */ 145 #define ZD_CR69 CTL_REG(0x0114) 146 #define ZD_CR70 CTL_REG(0x0118) 147 #define ZD_CR71 CTL_REG(0x011C) 148 #define ZD_CR72 CTL_REG(0x0120) 149 #define ZD_CR73 CTL_REG(0x0124) 150 #define ZD_CR74 CTL_REG(0x0128) 151 #define ZD_CR75 CTL_REG(0x012C) 152 #define ZD_CR76 CTL_REG(0x0130) 153 #define ZD_CR77 CTL_REG(0x0134) 154 #define ZD_CR78 CTL_REG(0x0138) 155 #define ZD_CR79 CTL_REG(0x013C) 156 #define ZD_CR80 CTL_REG(0x0140) 157 #define ZD_CR81 CTL_REG(0x0144) 158 #define ZD_CR82 CTL_REG(0x0148) 159 #define ZD_CR83 CTL_REG(0x014C) 160 #define ZD_CR84 CTL_REG(0x0150) 161 #define ZD_CR85 CTL_REG(0x0154) 162 #define ZD_CR86 CTL_REG(0x0158) 163 #define ZD_CR87 CTL_REG(0x015C) 164 #define ZD_CR88 CTL_REG(0x0160) 165 #define ZD_CR89 CTL_REG(0x0164) 166 #define ZD_CR90 CTL_REG(0x0168) 167 #define ZD_CR91 CTL_REG(0x016C) 168 #define ZD_CR92 CTL_REG(0x0170) 169 #define ZD_CR93 CTL_REG(0x0174) 170 #define ZD_CR94 CTL_REG(0x0178) 171 #define ZD_CR95 CTL_REG(0x017C) 172 #define ZD_CR96 CTL_REG(0x0180) 173 #define ZD_CR97 CTL_REG(0x0184) 174 #define ZD_CR98 CTL_REG(0x0188) 175 #define ZD_CR99 CTL_REG(0x018C) 176 #define ZD_CR100 CTL_REG(0x0190) 177 #define ZD_CR101 CTL_REG(0x0194) 178 #define ZD_CR102 CTL_REG(0x0198) 179 #define ZD_CR103 CTL_REG(0x019C) 180 #define ZD_CR104 CTL_REG(0x01A0) 181 #define ZD_CR105 CTL_REG(0x01A4) 182 #define ZD_CR106 CTL_REG(0x01A8) 183 #define ZD_CR107 CTL_REG(0x01AC) 184 #define ZD_CR108 CTL_REG(0x01B0) 185 #define ZD_CR109 CTL_REG(0x01B4) 186 #define ZD_CR110 CTL_REG(0x01B8) 187 #define ZD_CR111 CTL_REG(0x01BC) 188 #define ZD_CR112 CTL_REG(0x01C0) 189 #define ZD_CR113 CTL_REG(0x01C4) 190 #define ZD_CR114 CTL_REG(0x01C8) 191 #define ZD_CR115 CTL_REG(0x01CC) 192 #define ZD_CR116 CTL_REG(0x01D0) 193 #define ZD_CR117 CTL_REG(0x01D4) 194 #define ZD_CR118 CTL_REG(0x01D8) 195 #define ZD_CR119 CTL_REG(0x01DC) 196 #define ZD_CR120 CTL_REG(0x01E0) 197 #define ZD_CR121 CTL_REG(0x01E4) 198 #define ZD_CR122 CTL_REG(0x01E8) 199 #define ZD_CR123 CTL_REG(0x01EC) 200 #define ZD_CR124 CTL_REG(0x01F0) 201 #define ZD_CR125 CTL_REG(0x01F4) 202 #define ZD_CR126 CTL_REG(0x01F8) 203 #define ZD_CR127 CTL_REG(0x01FC) 204 #define ZD_CR128 CTL_REG(0x0200) 205 #define ZD_CR129 CTL_REG(0x0204) 206 #define ZD_CR130 CTL_REG(0x0208) 207 #define ZD_CR131 CTL_REG(0x020C) 208 #define ZD_CR132 CTL_REG(0x0210) 209 #define ZD_CR133 CTL_REG(0x0214) 210 #define ZD_CR134 CTL_REG(0x0218) 211 #define ZD_CR135 CTL_REG(0x021C) 212 #define ZD_CR136 CTL_REG(0x0220) 213 #define ZD_CR137 CTL_REG(0x0224) 214 #define ZD_CR138 CTL_REG(0x0228) 215 #define ZD_CR139 CTL_REG(0x022C) 216 #define ZD_CR140 CTL_REG(0x0230) 217 #define ZD_CR141 CTL_REG(0x0234) 218 #define ZD_CR142 CTL_REG(0x0238) 219 #define ZD_CR143 CTL_REG(0x023C) 220 #define ZD_CR144 CTL_REG(0x0240) 221 #define ZD_CR145 CTL_REG(0x0244) 222 #define ZD_CR146 CTL_REG(0x0248) 223 #define ZD_CR147 CTL_REG(0x024C) 224 #define ZD_CR148 CTL_REG(0x0250) 225 #define ZD_CR149 CTL_REG(0x0254) 226 #define ZD_CR150 CTL_REG(0x0258) 227 #define ZD_CR151 CTL_REG(0x025C) 228 #define ZD_CR152 CTL_REG(0x0260) 229 #define ZD_CR153 CTL_REG(0x0264) 230 #define ZD_CR154 CTL_REG(0x0268) 231 #define ZD_CR155 CTL_REG(0x026C) 232 #define ZD_CR156 CTL_REG(0x0270) 233 #define ZD_CR157 CTL_REG(0x0274) 234 #define ZD_CR158 CTL_REG(0x0278) 235 #define ZD_CR159 CTL_REG(0x027C) 236 #define ZD_CR160 CTL_REG(0x0280) 237 #define ZD_CR161 CTL_REG(0x0284) 238 #define ZD_CR162 CTL_REG(0x0288) 239 #define ZD_CR163 CTL_REG(0x028C) 240 #define ZD_CR164 CTL_REG(0x0290) 241 #define ZD_CR165 CTL_REG(0x0294) 242 #define ZD_CR166 CTL_REG(0x0298) 243 #define ZD_CR167 CTL_REG(0x029C) 244 #define ZD_CR168 CTL_REG(0x02A0) 245 #define ZD_CR169 CTL_REG(0x02A4) 246 #define ZD_CR170 CTL_REG(0x02A8) 247 #define ZD_CR171 CTL_REG(0x02AC) 248 #define ZD_CR172 CTL_REG(0x02B0) 249 #define ZD_CR173 CTL_REG(0x02B4) 250 #define ZD_CR174 CTL_REG(0x02B8) 251 #define ZD_CR175 CTL_REG(0x02BC) 252 #define ZD_CR176 CTL_REG(0x02C0) 253 #define ZD_CR177 CTL_REG(0x02C4) 254 #define ZD_CR178 CTL_REG(0x02C8) 255 #define ZD_CR179 CTL_REG(0x02CC) 256 #define ZD_CR180 CTL_REG(0x02D0) 257 #define ZD_CR181 CTL_REG(0x02D4) 258 #define ZD_CR182 CTL_REG(0x02D8) 259 #define ZD_CR183 CTL_REG(0x02DC) 260 #define ZD_CR184 CTL_REG(0x02E0) 261 #define ZD_CR185 CTL_REG(0x02E4) 262 #define ZD_CR186 CTL_REG(0x02E8) 263 #define ZD_CR187 CTL_REG(0x02EC) 264 #define ZD_CR188 CTL_REG(0x02F0) 265 #define ZD_CR189 CTL_REG(0x02F4) 266 #define ZD_CR190 CTL_REG(0x02F8) 267 #define ZD_CR191 CTL_REG(0x02FC) 268 #define ZD_CR192 CTL_REG(0x0300) 269 #define ZD_CR193 CTL_REG(0x0304) 270 #define ZD_CR194 CTL_REG(0x0308) 271 #define ZD_CR195 CTL_REG(0x030C) 272 #define ZD_CR196 CTL_REG(0x0310) 273 #define ZD_CR197 CTL_REG(0x0314) 274 #define ZD_CR198 CTL_REG(0x0318) 275 #define ZD_CR199 CTL_REG(0x031C) 276 #define ZD_CR200 CTL_REG(0x0320) 277 #define ZD_CR201 CTL_REG(0x0324) 278 #define ZD_CR202 CTL_REG(0x0328) 279 #define ZD_CR203 CTL_REG(0x032C) /* I2C bus template value & flash 280 * control 281 */ 282 #define ZD_CR204 CTL_REG(0x0330) 283 #define ZD_CR205 CTL_REG(0x0334) 284 #define ZD_CR206 CTL_REG(0x0338) 285 #define ZD_CR207 CTL_REG(0x033C) 286 #define ZD_CR208 CTL_REG(0x0340) 287 #define ZD_CR209 CTL_REG(0x0344) 288 #define ZD_CR210 CTL_REG(0x0348) 289 #define ZD_CR211 CTL_REG(0x034C) 290 #define ZD_CR212 CTL_REG(0x0350) 291 #define ZD_CR213 CTL_REG(0x0354) 292 #define ZD_CR214 CTL_REG(0x0358) 293 #define ZD_CR215 CTL_REG(0x035C) 294 #define ZD_CR216 CTL_REG(0x0360) 295 #define ZD_CR217 CTL_REG(0x0364) 296 #define ZD_CR218 CTL_REG(0x0368) 297 #define ZD_CR219 CTL_REG(0x036C) 298 #define ZD_CR220 CTL_REG(0x0370) 299 #define ZD_CR221 CTL_REG(0x0374) 300 #define ZD_CR222 CTL_REG(0x0378) 301 #define ZD_CR223 CTL_REG(0x037C) 302 #define ZD_CR224 CTL_REG(0x0380) 303 #define ZD_CR225 CTL_REG(0x0384) 304 #define ZD_CR226 CTL_REG(0x0388) 305 #define ZD_CR227 CTL_REG(0x038C) 306 #define ZD_CR228 CTL_REG(0x0390) 307 #define ZD_CR229 CTL_REG(0x0394) 308 #define ZD_CR230 CTL_REG(0x0398) 309 #define ZD_CR231 CTL_REG(0x039C) 310 #define ZD_CR232 CTL_REG(0x03A0) 311 #define ZD_CR233 CTL_REG(0x03A4) 312 #define ZD_CR234 CTL_REG(0x03A8) 313 #define ZD_CR235 CTL_REG(0x03AC) 314 #define ZD_CR236 CTL_REG(0x03B0) 315 316 #define ZD_CR240 CTL_REG(0x03C0) 317 /* bit 7: host-controlled RF register writes 318 * ZD_CR241-ZD_CR245: for hardware controlled writing of RF bits, not needed for 319 * USB 320 */ 321 #define ZD_CR241 CTL_REG(0x03C4) 322 #define ZD_CR242 CTL_REG(0x03C8) 323 #define ZD_CR243 CTL_REG(0x03CC) 324 #define ZD_CR244 CTL_REG(0x03D0) 325 #define ZD_CR245 CTL_REG(0x03D4) 326 327 #define ZD_CR251 CTL_REG(0x03EC) /* only used for activation and 328 * deactivation of Airoha RFs AL2230 329 * and AL7230B 330 */ 331 #define ZD_CR252 CTL_REG(0x03F0) 332 #define ZD_CR253 CTL_REG(0x03F4) 333 #define ZD_CR254 CTL_REG(0x03F8) 334 #define ZD_CR255 CTL_REG(0x03FC) 335 336 #define CR_MAX_PHY_REG 255 337 338 /* Taken from the ZYDAS driver, not all of them are relevant for the ZD1211 339 * driver. 340 */ 341 342 #define CR_RF_IF_CLK CTL_REG(0x0400) 343 #define CR_RF_IF_DATA CTL_REG(0x0404) 344 #define CR_PE1_PE2 CTL_REG(0x0408) 345 #define CR_PE2_DLY CTL_REG(0x040C) 346 #define CR_LE1 CTL_REG(0x0410) 347 #define CR_LE2 CTL_REG(0x0414) 348 /* Seems to enable/disable GPI (General Purpose IO?) */ 349 #define CR_GPI_EN CTL_REG(0x0418) 350 #define CR_RADIO_PD CTL_REG(0x042C) 351 #define CR_RF2948_PD CTL_REG(0x042C) 352 #define CR_ENABLE_PS_MANUAL_AGC CTL_REG(0x043C) 353 #define CR_CONFIG_PHILIPS CTL_REG(0x0440) 354 #define CR_SA2400_SER_AP CTL_REG(0x0444) 355 #define CR_I2C_WRITE CTL_REG(0x0444) 356 #define CR_SA2400_SER_RP CTL_REG(0x0448) 357 #define CR_RADIO_PE CTL_REG(0x0458) 358 #define CR_RST_BUS_MASTER CTL_REG(0x045C) 359 #define CR_RFCFG CTL_REG(0x0464) 360 #define CR_HSTSCHG CTL_REG(0x046C) 361 #define CR_PHY_ON CTL_REG(0x0474) 362 #define CR_RX_DELAY CTL_REG(0x0478) 363 #define CR_RX_PE_DELAY CTL_REG(0x047C) 364 #define CR_GPIO_1 CTL_REG(0x0490) 365 #define CR_GPIO_2 CTL_REG(0x0494) 366 #define CR_EncryBufMux CTL_REG(0x04A8) 367 #define CR_PS_CTRL CTL_REG(0x0500) 368 #define CR_ADDA_PWR_DWN CTL_REG(0x0504) 369 #define CR_ADDA_MBIAS_WARMTIME CTL_REG(0x0508) 370 #define CR_MAC_PS_STATE CTL_REG(0x050C) 371 372 #define CR_INTERRUPT CTL_REG(0x0510) 373 #define INT_TX_COMPLETE (1 << 0) 374 #define INT_RX_COMPLETE (1 << 1) 375 #define INT_RETRY_FAIL (1 << 2) 376 #define INT_WAKEUP (1 << 3) 377 #define INT_DTIM_NOTIFY (1 << 5) 378 #define INT_CFG_NEXT_BCN (1 << 6) 379 #define INT_BUS_ABORT (1 << 7) 380 #define INT_TX_FIFO_READY (1 << 8) 381 #define INT_UART (1 << 9) 382 #define INT_TX_COMPLETE_EN (1 << 16) 383 #define INT_RX_COMPLETE_EN (1 << 17) 384 #define INT_RETRY_FAIL_EN (1 << 18) 385 #define INT_WAKEUP_EN (1 << 19) 386 #define INT_DTIM_NOTIFY_EN (1 << 21) 387 #define INT_CFG_NEXT_BCN_EN (1 << 22) 388 #define INT_BUS_ABORT_EN (1 << 23) 389 #define INT_TX_FIFO_READY_EN (1 << 24) 390 #define INT_UART_EN (1 << 25) 391 392 #define CR_TSF_LOW_PART CTL_REG(0x0514) 393 #define CR_TSF_HIGH_PART CTL_REG(0x0518) 394 395 /* Following three values are in time units (1024us) 396 * Following condition must be met: 397 * atim < tbtt < bcn 398 */ 399 #define CR_ATIM_WND_PERIOD CTL_REG(0x051C) 400 #define CR_BCN_INTERVAL CTL_REG(0x0520) 401 #define CR_PRE_TBTT CTL_REG(0x0524) 402 /* in units of TU(1024us) */ 403 404 /* for UART support */ 405 #define CR_UART_RBR_THR_DLL CTL_REG(0x0540) 406 #define CR_UART_DLM_IER CTL_REG(0x0544) 407 #define CR_UART_IIR_FCR CTL_REG(0x0548) 408 #define CR_UART_LCR CTL_REG(0x054c) 409 #define CR_UART_MCR CTL_REG(0x0550) 410 #define CR_UART_LSR CTL_REG(0x0554) 411 #define CR_UART_MSR CTL_REG(0x0558) 412 #define CR_UART_ECR CTL_REG(0x055c) 413 #define CR_UART_STATUS CTL_REG(0x0560) 414 415 #define CR_PCI_TX_ADDR_P1 CTL_REG(0x0600) 416 #define CR_PCI_TX_AddR_P2 CTL_REG(0x0604) 417 #define CR_PCI_RX_AddR_P1 CTL_REG(0x0608) 418 #define CR_PCI_RX_AddR_P2 CTL_REG(0x060C) 419 420 /* must be overwritten if custom MAC address will be used */ 421 #define CR_MAC_ADDR_P1 CTL_REG(0x0610) 422 #define CR_MAC_ADDR_P2 CTL_REG(0x0614) 423 #define CR_BSSID_P1 CTL_REG(0x0618) 424 #define CR_BSSID_P2 CTL_REG(0x061C) 425 #define CR_BCN_PLCP_CFG CTL_REG(0x0620) 426 427 /* Group hash table for filtering incoming packets. 428 * 429 * The group hash table is 64 bit large and split over two parts. The first 430 * part is the lower part. The upper 6 bits of the last byte of the target 431 * address are used as index. Packets are received if the hash table bit is 432 * set. This is used for multicast handling, but for broadcasts (address 433 * ff:ff:ff:ff:ff:ff) the highest bit in the second table must also be set. 434 */ 435 #define CR_GROUP_HASH_P1 CTL_REG(0x0624) 436 #define CR_GROUP_HASH_P2 CTL_REG(0x0628) 437 438 #define CR_RX_TIMEOUT CTL_REG(0x062C) 439 440 /* Basic rates supported by the BSS. When producing ACK or CTS messages, the 441 * device will use a rate in this table that is less than or equal to the rate 442 * of the incoming frame which prompted the response. */ 443 #define CR_BASIC_RATE_TBL CTL_REG(0x0630) 444 #define CR_RATE_1M (1 << 0) /* 802.11b */ 445 #define CR_RATE_2M (1 << 1) /* 802.11b */ 446 #define CR_RATE_5_5M (1 << 2) /* 802.11b */ 447 #define CR_RATE_11M (1 << 3) /* 802.11b */ 448 #define CR_RATE_6M (1 << 8) /* 802.11g */ 449 #define CR_RATE_9M (1 << 9) /* 802.11g */ 450 #define CR_RATE_12M (1 << 10) /* 802.11g */ 451 #define CR_RATE_18M (1 << 11) /* 802.11g */ 452 #define CR_RATE_24M (1 << 12) /* 802.11g */ 453 #define CR_RATE_36M (1 << 13) /* 802.11g */ 454 #define CR_RATE_48M (1 << 14) /* 802.11g */ 455 #define CR_RATE_54M (1 << 15) /* 802.11g */ 456 #define CR_RATES_80211G 0xff00 457 #define CR_RATES_80211B 0x000f 458 459 /* Mandatory rates required in the BSS. When producing ACK or CTS messages, if 460 * the device could not find an appropriate rate in CR_BASIC_RATE_TBL, it will 461 * look for a rate in this table that is less than or equal to the rate of 462 * the incoming frame. */ 463 #define CR_MANDATORY_RATE_TBL CTL_REG(0x0634) 464 #define CR_RTS_CTS_RATE CTL_REG(0x0638) 465 466 /* These are all bit indexes in CR_RTS_CTS_RATE, so remember to shift. */ 467 #define RTSCTS_SH_RTS_RATE 0 468 #define RTSCTS_SH_EXP_CTS_RATE 4 469 #define RTSCTS_SH_RTS_MOD_TYPE 8 470 #define RTSCTS_SH_RTS_PMB_TYPE 9 471 #define RTSCTS_SH_CTS_RATE 16 472 #define RTSCTS_SH_CTS_MOD_TYPE 24 473 #define RTSCTS_SH_CTS_PMB_TYPE 25 474 475 #define CR_WEP_PROTECT CTL_REG(0x063C) 476 #define CR_RX_THRESHOLD CTL_REG(0x0640) 477 478 /* register for controlling the LEDS */ 479 #define CR_LED CTL_REG(0x0644) 480 /* masks for controlling LEDs */ 481 #define LED1 (1 << 8) 482 #define LED2 (1 << 9) 483 #define LED_SW (1 << 10) 484 485 /* Seems to indicate that the configuration is over. 486 */ 487 #define CR_AFTER_PNP CTL_REG(0x0648) 488 #define CR_ACK_TIME_80211 CTL_REG(0x0658) 489 490 #define CR_RX_OFFSET CTL_REG(0x065c) 491 492 #define CR_BCN_LENGTH CTL_REG(0x0664) 493 #define CR_PHY_DELAY CTL_REG(0x066C) 494 #define CR_BCN_FIFO CTL_REG(0x0670) 495 #define CR_SNIFFER_ON CTL_REG(0x0674) 496 497 #define CR_ENCRYPTION_TYPE CTL_REG(0x0678) 498 #define NO_WEP 0 499 #define WEP64 1 500 #define WEP128 5 501 #define WEP256 6 502 #define ENC_SNIFFER 8 503 504 #define CR_ZD1211_RETRY_MAX CTL_REG(0x067C) 505 506 #define CR_REG1 CTL_REG(0x0680) 507 /* Setting the bit UNLOCK_PHY_REGS disallows the write access to physical 508 * registers, so one could argue it is a LOCK bit. But calling it 509 * LOCK_PHY_REGS makes it confusing. 510 */ 511 #define UNLOCK_PHY_REGS (1 << 7) 512 513 #define CR_DEVICE_STATE CTL_REG(0x0684) 514 #define CR_UNDERRUN_CNT CTL_REG(0x0688) 515 516 #define CR_RX_FILTER CTL_REG(0x068c) 517 #define RX_FILTER_ASSOC_REQUEST (1 << 0) 518 #define RX_FILTER_ASSOC_RESPONSE (1 << 1) 519 #define RX_FILTER_REASSOC_REQUEST (1 << 2) 520 #define RX_FILTER_REASSOC_RESPONSE (1 << 3) 521 #define RX_FILTER_PROBE_REQUEST (1 << 4) 522 #define RX_FILTER_PROBE_RESPONSE (1 << 5) 523 /* bits 6 and 7 reserved */ 524 #define RX_FILTER_BEACON (1 << 8) 525 #define RX_FILTER_ATIM (1 << 9) 526 #define RX_FILTER_DISASSOC (1 << 10) 527 #define RX_FILTER_AUTH (1 << 11) 528 #define RX_FILTER_DEAUTH (1 << 12) 529 #define RX_FILTER_PSPOLL (1 << 26) 530 #define RX_FILTER_RTS (1 << 27) 531 #define RX_FILTER_CTS (1 << 28) 532 #define RX_FILTER_ACK (1 << 29) 533 #define RX_FILTER_CFEND (1 << 30) 534 #define RX_FILTER_CFACK (1 << 31) 535 536 /* Enable bits for all frames you are interested in. */ 537 #define STA_RX_FILTER (RX_FILTER_ASSOC_REQUEST | RX_FILTER_ASSOC_RESPONSE | \ 538 RX_FILTER_REASSOC_REQUEST | RX_FILTER_REASSOC_RESPONSE | \ 539 RX_FILTER_PROBE_REQUEST | RX_FILTER_PROBE_RESPONSE | \ 540 (0x3 << 6) /* vendor driver sets these reserved bits */ | \ 541 RX_FILTER_BEACON | RX_FILTER_ATIM | RX_FILTER_DISASSOC | \ 542 RX_FILTER_AUTH | RX_FILTER_DEAUTH | \ 543 (0x7 << 13) /* vendor driver sets these reserved bits */ | \ 544 RX_FILTER_PSPOLL | RX_FILTER_ACK) /* 0x2400ffff */ 545 546 #define RX_FILTER_CTRL (RX_FILTER_RTS | RX_FILTER_CTS | \ 547 RX_FILTER_CFEND | RX_FILTER_CFACK) 548 549 #define BCN_MODE_AP 0x1000000 550 #define BCN_MODE_IBSS 0x2000000 551 552 /* Monitor mode sets filter to 0xfffff */ 553 554 #define CR_ACK_TIMEOUT_EXT CTL_REG(0x0690) 555 #define CR_BCN_FIFO_SEMAPHORE CTL_REG(0x0694) 556 557 #define CR_IFS_VALUE CTL_REG(0x0698) 558 #define IFS_VALUE_DIFS_SH 0 559 #define IFS_VALUE_EIFS_SH 12 560 #define IFS_VALUE_SIFS_SH 24 561 #define IFS_VALUE_DEFAULT (( 50 << IFS_VALUE_DIFS_SH) | \ 562 (1148 << IFS_VALUE_EIFS_SH) | \ 563 ( 10 << IFS_VALUE_SIFS_SH)) 564 565 #define CR_RX_TIME_OUT CTL_REG(0x069C) 566 #define CR_TOTAL_RX_FRM CTL_REG(0x06A0) 567 #define CR_CRC32_CNT CTL_REG(0x06A4) 568 #define CR_CRC16_CNT CTL_REG(0x06A8) 569 #define CR_DECRYPTION_ERR_UNI CTL_REG(0x06AC) 570 #define CR_RX_FIFO_OVERRUN CTL_REG(0x06B0) 571 572 #define CR_DECRYPTION_ERR_MUL CTL_REG(0x06BC) 573 574 #define CR_NAV_CNT CTL_REG(0x06C4) 575 #define CR_NAV_CCA CTL_REG(0x06C8) 576 #define CR_RETRY_CNT CTL_REG(0x06CC) 577 578 #define CR_READ_TCB_ADDR CTL_REG(0x06E8) 579 #define CR_READ_RFD_ADDR CTL_REG(0x06EC) 580 #define CR_CWMIN_CWMAX CTL_REG(0x06F0) 581 #define CR_TOTAL_TX_FRM CTL_REG(0x06F4) 582 583 /* CAM: Continuous Access Mode (power management) */ 584 #define CR_CAM_MODE CTL_REG(0x0700) 585 #define MODE_IBSS 0x0 586 #define MODE_AP 0x1 587 #define MODE_STA 0x2 588 #define MODE_AP_WDS 0x3 589 590 #define CR_CAM_ROLL_TB_LOW CTL_REG(0x0704) 591 #define CR_CAM_ROLL_TB_HIGH CTL_REG(0x0708) 592 #define CR_CAM_ADDRESS CTL_REG(0x070C) 593 #define CR_CAM_DATA CTL_REG(0x0710) 594 595 #define CR_ROMDIR CTL_REG(0x0714) 596 597 #define CR_DECRY_ERR_FLG_LOW CTL_REG(0x0714) 598 #define CR_DECRY_ERR_FLG_HIGH CTL_REG(0x0718) 599 600 #define CR_WEPKEY0 CTL_REG(0x0720) 601 #define CR_WEPKEY1 CTL_REG(0x0724) 602 #define CR_WEPKEY2 CTL_REG(0x0728) 603 #define CR_WEPKEY3 CTL_REG(0x072C) 604 #define CR_WEPKEY4 CTL_REG(0x0730) 605 #define CR_WEPKEY5 CTL_REG(0x0734) 606 #define CR_WEPKEY6 CTL_REG(0x0738) 607 #define CR_WEPKEY7 CTL_REG(0x073C) 608 #define CR_WEPKEY8 CTL_REG(0x0740) 609 #define CR_WEPKEY9 CTL_REG(0x0744) 610 #define CR_WEPKEY10 CTL_REG(0x0748) 611 #define CR_WEPKEY11 CTL_REG(0x074C) 612 #define CR_WEPKEY12 CTL_REG(0x0750) 613 #define CR_WEPKEY13 CTL_REG(0x0754) 614 #define CR_WEPKEY14 CTL_REG(0x0758) 615 #define CR_WEPKEY15 CTL_REG(0x075c) 616 #define CR_TKIP_MODE CTL_REG(0x0760) 617 618 #define CR_EEPROM_PROTECT0 CTL_REG(0x0758) 619 #define CR_EEPROM_PROTECT1 CTL_REG(0x075C) 620 621 #define CR_DBG_FIFO_RD CTL_REG(0x0800) 622 #define CR_DBG_SELECT CTL_REG(0x0804) 623 #define CR_FIFO_Length CTL_REG(0x0808) 624 625 626 #define CR_RSSI_MGC CTL_REG(0x0810) 627 628 #define CR_PON CTL_REG(0x0818) 629 #define CR_RX_ON CTL_REG(0x081C) 630 #define CR_TX_ON CTL_REG(0x0820) 631 #define CR_CHIP_EN CTL_REG(0x0824) 632 #define CR_LO_SW CTL_REG(0x0828) 633 #define CR_TXRX_SW CTL_REG(0x082C) 634 #define CR_S_MD CTL_REG(0x0830) 635 636 #define CR_USB_DEBUG_PORT CTL_REG(0x0888) 637 #define CR_ZD1211B_CWIN_MAX_MIN_AC0 CTL_REG(0x0b00) 638 #define CR_ZD1211B_CWIN_MAX_MIN_AC1 CTL_REG(0x0b04) 639 #define CR_ZD1211B_CWIN_MAX_MIN_AC2 CTL_REG(0x0b08) 640 #define CR_ZD1211B_CWIN_MAX_MIN_AC3 CTL_REG(0x0b0c) 641 #define CR_ZD1211B_AIFS_CTL1 CTL_REG(0x0b10) 642 #define CR_ZD1211B_AIFS_CTL2 CTL_REG(0x0b14) 643 #define CR_ZD1211B_TXOP CTL_REG(0x0b20) 644 #define CR_ZD1211B_RETRY_MAX CTL_REG(0x0b28) 645 646 /* Value for CR_ZD1211_RETRY_MAX & CR_ZD1211B_RETRY_MAX. Vendor driver uses 2, 647 * we use 0. The first rate is tried (count+2), then all next rates are tried 648 * twice, until 1 Mbits is tried. */ 649 #define ZD1211_RETRY_COUNT 0 650 #define ZD1211B_RETRY_COUNT \ 651 (ZD1211_RETRY_COUNT << 0)| \ 652 (ZD1211_RETRY_COUNT << 8)| \ 653 (ZD1211_RETRY_COUNT << 16)| \ 654 (ZD1211_RETRY_COUNT << 24) 655 656 /* Used to detect PLL lock */ 657 #define UW2453_INTR_REG ((zd_addr_t)0x85c1) 658 659 #define CWIN_SIZE 0x007f043f 660 661 662 #define HWINT_ENABLED \ 663 (INT_TX_COMPLETE_EN| \ 664 INT_RX_COMPLETE_EN| \ 665 INT_RETRY_FAIL_EN| \ 666 INT_WAKEUP_EN| \ 667 INT_CFG_NEXT_BCN_EN) 668 669 #define HWINT_DISABLED 0 670 671 #define E2P_PWR_INT_GUARD 8 672 #define E2P_CHANNEL_COUNT 14 673 674 /* If you compare this addresses with the ZYDAS orignal driver, please notify 675 * that we use word mapping for the EEPROM. 676 */ 677 678 /* 679 * Upper 16 bit contains the regulatory domain. 680 */ 681 #define E2P_SUBID E2P_DATA(0x00) 682 #define E2P_POD E2P_DATA(0x02) 683 #define E2P_MAC_ADDR_P1 E2P_DATA(0x04) 684 #define E2P_MAC_ADDR_P2 E2P_DATA(0x06) 685 #define E2P_PWR_CAL_VALUE1 E2P_DATA(0x08) 686 #define E2P_PWR_CAL_VALUE2 E2P_DATA(0x0a) 687 #define E2P_PWR_CAL_VALUE3 E2P_DATA(0x0c) 688 #define E2P_PWR_CAL_VALUE4 E2P_DATA(0x0e) 689 #define E2P_PWR_INT_VALUE1 E2P_DATA(0x10) 690 #define E2P_PWR_INT_VALUE2 E2P_DATA(0x12) 691 #define E2P_PWR_INT_VALUE3 E2P_DATA(0x14) 692 #define E2P_PWR_INT_VALUE4 E2P_DATA(0x16) 693 694 /* Contains a bit for each allowed channel. It gives for Europe (ETSI 0x30) 695 * also only 11 channels. */ 696 #define E2P_ALLOWED_CHANNEL E2P_DATA(0x18) 697 698 #define E2P_DEVICE_VER E2P_DATA(0x20) 699 #define E2P_PHY_REG E2P_DATA(0x25) 700 #define E2P_36M_CAL_VALUE1 E2P_DATA(0x28) 701 #define E2P_36M_CAL_VALUE2 E2P_DATA(0x2a) 702 #define E2P_36M_CAL_VALUE3 E2P_DATA(0x2c) 703 #define E2P_36M_CAL_VALUE4 E2P_DATA(0x2e) 704 #define E2P_11A_INT_VALUE1 E2P_DATA(0x30) 705 #define E2P_11A_INT_VALUE2 E2P_DATA(0x32) 706 #define E2P_11A_INT_VALUE3 E2P_DATA(0x34) 707 #define E2P_11A_INT_VALUE4 E2P_DATA(0x36) 708 #define E2P_48M_CAL_VALUE1 E2P_DATA(0x38) 709 #define E2P_48M_CAL_VALUE2 E2P_DATA(0x3a) 710 #define E2P_48M_CAL_VALUE3 E2P_DATA(0x3c) 711 #define E2P_48M_CAL_VALUE4 E2P_DATA(0x3e) 712 #define E2P_48M_INT_VALUE1 E2P_DATA(0x40) 713 #define E2P_48M_INT_VALUE2 E2P_DATA(0x42) 714 #define E2P_48M_INT_VALUE3 E2P_DATA(0x44) 715 #define E2P_48M_INT_VALUE4 E2P_DATA(0x46) 716 #define E2P_54M_CAL_VALUE1 E2P_DATA(0x48) /* ??? */ 717 #define E2P_54M_CAL_VALUE2 E2P_DATA(0x4a) 718 #define E2P_54M_CAL_VALUE3 E2P_DATA(0x4c) 719 #define E2P_54M_CAL_VALUE4 E2P_DATA(0x4e) 720 #define E2P_54M_INT_VALUE1 E2P_DATA(0x50) 721 #define E2P_54M_INT_VALUE2 E2P_DATA(0x52) 722 #define E2P_54M_INT_VALUE3 E2P_DATA(0x54) 723 #define E2P_54M_INT_VALUE4 E2P_DATA(0x56) 724 725 /* This word contains the base address of the FW_REG_ registers below */ 726 #define FWRAW_REGS_ADDR FWRAW_DATA(0x1d) 727 728 /* All 16 bit values, offset from the address in FWRAW_REGS_ADDR */ 729 enum { 730 FW_REG_FIRMWARE_VER = 0, 731 /* non-zero if USB high speed connection */ 732 FW_REG_USB_SPEED = 1, 733 FW_REG_FIX_TX_RATE = 2, 734 /* Seems to be able to control LEDs over the firmware */ 735 FW_REG_LED_LINK_STATUS = 3, 736 FW_REG_SOFT_RESET = 4, 737 FW_REG_FLASH_CHK = 5, 738 }; 739 740 /* Values for FW_LINK_STATUS */ 741 #define FW_LINK_OFF 0x0 742 #define FW_LINK_TX 0x1 743 /* 0x2 - link led on? */ 744 745 enum { 746 /* indices for ofdm_cal_values */ 747 OFDM_36M_INDEX = 0, 748 OFDM_48M_INDEX = 1, 749 OFDM_54M_INDEX = 2, 750 }; 751 752 struct zd_chip { 753 struct zd_usb usb; 754 struct zd_rf rf; 755 struct mutex mutex; 756 /* Base address of FW_REG_ registers */ 757 zd_addr_t fw_regs_base; 758 /* EepSetPoint in the vendor driver */ 759 u8 pwr_cal_values[E2P_CHANNEL_COUNT]; 760 /* integration values in the vendor driver */ 761 u8 pwr_int_values[E2P_CHANNEL_COUNT]; 762 /* SetPointOFDM in the vendor driver */ 763 u8 ofdm_cal_values[3][E2P_CHANNEL_COUNT]; 764 u16 link_led; 765 unsigned int pa_type:4, 766 patch_cck_gain:1, patch_cr157:1, patch_6m_band_edge:1, 767 new_phy_layout:1, al2230s_bit:1, 768 supports_tx_led:1; 769 }; 770 zd_usb_to_chip(struct zd_usb * usb)771 static inline struct zd_chip *zd_usb_to_chip(struct zd_usb *usb) 772 { 773 return container_of(usb, struct zd_chip, usb); 774 } 775 zd_rf_to_chip(struct zd_rf * rf)776 static inline struct zd_chip *zd_rf_to_chip(struct zd_rf *rf) 777 { 778 return container_of(rf, struct zd_chip, rf); 779 } 780 781 #define zd_chip_dev(chip) (&(chip)->usb.intf->dev) 782 783 void zd_chip_init(struct zd_chip *chip, 784 struct ieee80211_hw *hw, 785 struct usb_interface *intf); 786 void zd_chip_clear(struct zd_chip *chip); 787 int zd_chip_read_mac_addr_fw(struct zd_chip *chip, u8 *addr); 788 int zd_chip_init_hw(struct zd_chip *chip); 789 int zd_chip_reset(struct zd_chip *chip); 790 zd_chip_is_zd1211b(struct zd_chip * chip)791 static inline int zd_chip_is_zd1211b(struct zd_chip *chip) 792 { 793 return chip->usb.is_zd1211b; 794 } 795 zd_ioread16v_locked(struct zd_chip * chip,u16 * values,const zd_addr_t * addresses,unsigned int count)796 static inline int zd_ioread16v_locked(struct zd_chip *chip, u16 *values, 797 const zd_addr_t *addresses, 798 unsigned int count) 799 { 800 ZD_ASSERT(mutex_is_locked(&chip->mutex)); 801 return zd_usb_ioread16v(&chip->usb, values, addresses, count); 802 } 803 zd_ioread16_locked(struct zd_chip * chip,u16 * value,const zd_addr_t addr)804 static inline int zd_ioread16_locked(struct zd_chip *chip, u16 *value, 805 const zd_addr_t addr) 806 { 807 ZD_ASSERT(mutex_is_locked(&chip->mutex)); 808 return zd_usb_ioread16(&chip->usb, value, addr); 809 } 810 811 int zd_ioread32v_locked(struct zd_chip *chip, u32 *values, 812 const zd_addr_t *addresses, unsigned int count); 813 zd_ioread32_locked(struct zd_chip * chip,u32 * value,const zd_addr_t addr)814 static inline int zd_ioread32_locked(struct zd_chip *chip, u32 *value, 815 const zd_addr_t addr) 816 { 817 return zd_ioread32v_locked(chip, value, &addr, 1); 818 } 819 zd_iowrite16_locked(struct zd_chip * chip,u16 value,zd_addr_t addr)820 static inline int zd_iowrite16_locked(struct zd_chip *chip, u16 value, 821 zd_addr_t addr) 822 { 823 struct zd_ioreq16 ioreq; 824 825 ZD_ASSERT(mutex_is_locked(&chip->mutex)); 826 ioreq.addr = addr; 827 ioreq.value = value; 828 829 return zd_usb_iowrite16v(&chip->usb, &ioreq, 1); 830 } 831 832 int zd_iowrite16a_locked(struct zd_chip *chip, 833 const struct zd_ioreq16 *ioreqs, unsigned int count); 834 835 int _zd_iowrite32v_locked(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs, 836 unsigned int count); 837 zd_iowrite32_locked(struct zd_chip * chip,u32 value,zd_addr_t addr)838 static inline int zd_iowrite32_locked(struct zd_chip *chip, u32 value, 839 zd_addr_t addr) 840 { 841 struct zd_ioreq32 ioreq; 842 843 ioreq.addr = addr; 844 ioreq.value = value; 845 846 return _zd_iowrite32v_locked(chip, &ioreq, 1); 847 } 848 849 int zd_iowrite32a_locked(struct zd_chip *chip, 850 const struct zd_ioreq32 *ioreqs, unsigned int count); 851 zd_rfwrite_locked(struct zd_chip * chip,u32 value,u8 bits)852 static inline int zd_rfwrite_locked(struct zd_chip *chip, u32 value, u8 bits) 853 { 854 ZD_ASSERT(mutex_is_locked(&chip->mutex)); 855 return zd_usb_rfwrite(&chip->usb, value, bits); 856 } 857 858 int zd_rfwrite_cr_locked(struct zd_chip *chip, u32 value); 859 860 int zd_rfwritev_locked(struct zd_chip *chip, 861 const u32* values, unsigned int count, u8 bits); 862 int zd_rfwritev_cr_locked(struct zd_chip *chip, 863 const u32* values, unsigned int count); 864 865 /* Locking functions for reading and writing registers. 866 * The different parameters are intentional. 867 */ 868 int zd_ioread16(struct zd_chip *chip, zd_addr_t addr, u16 *value); 869 int zd_iowrite16(struct zd_chip *chip, zd_addr_t addr, u16 value); 870 int zd_ioread32(struct zd_chip *chip, zd_addr_t addr, u32 *value); 871 int zd_iowrite32(struct zd_chip *chip, zd_addr_t addr, u32 value); 872 int zd_ioread32v(struct zd_chip *chip, const zd_addr_t *addresses, 873 u32 *values, unsigned int count); 874 int zd_iowrite32a(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs, 875 unsigned int count); 876 877 int zd_chip_set_channel(struct zd_chip *chip, u8 channel); _zd_chip_get_channel(struct zd_chip * chip)878 static inline u8 _zd_chip_get_channel(struct zd_chip *chip) 879 { 880 return chip->rf.channel; 881 } 882 u8 zd_chip_get_channel(struct zd_chip *chip); 883 int zd_read_regdomain(struct zd_chip *chip, u8 *regdomain); 884 int zd_write_mac_addr(struct zd_chip *chip, const u8 *mac_addr); 885 int zd_write_bssid(struct zd_chip *chip, const u8 *bssid); 886 int zd_chip_switch_radio_on(struct zd_chip *chip); 887 int zd_chip_switch_radio_off(struct zd_chip *chip); 888 int zd_chip_enable_int(struct zd_chip *chip); 889 void zd_chip_disable_int(struct zd_chip *chip); 890 int zd_chip_enable_rxtx(struct zd_chip *chip); 891 void zd_chip_disable_rxtx(struct zd_chip *chip); 892 int zd_chip_enable_hwint(struct zd_chip *chip); 893 int zd_chip_disable_hwint(struct zd_chip *chip); 894 int zd_chip_generic_patch_6m_band(struct zd_chip *chip, int channel); 895 int zd_chip_set_rts_cts_rate_locked(struct zd_chip *chip, int preamble); 896 zd_get_encryption_type(struct zd_chip * chip,u32 * type)897 static inline int zd_get_encryption_type(struct zd_chip *chip, u32 *type) 898 { 899 return zd_ioread32(chip, CR_ENCRYPTION_TYPE, type); 900 } 901 zd_set_encryption_type(struct zd_chip * chip,u32 type)902 static inline int zd_set_encryption_type(struct zd_chip *chip, u32 type) 903 { 904 return zd_iowrite32(chip, CR_ENCRYPTION_TYPE, type); 905 } 906 zd_chip_get_basic_rates(struct zd_chip * chip,u16 * cr_rates)907 static inline int zd_chip_get_basic_rates(struct zd_chip *chip, u16 *cr_rates) 908 { 909 return zd_ioread16(chip, CR_BASIC_RATE_TBL, cr_rates); 910 } 911 912 int zd_chip_set_basic_rates(struct zd_chip *chip, u16 cr_rates); 913 914 int zd_chip_lock_phy_regs(struct zd_chip *chip); 915 int zd_chip_unlock_phy_regs(struct zd_chip *chip); 916 917 enum led_status { 918 ZD_LED_OFF = 0, 919 ZD_LED_SCANNING = 1, 920 ZD_LED_ASSOCIATED = 2, 921 }; 922 923 int zd_chip_control_leds(struct zd_chip *chip, enum led_status status); 924 925 int zd_set_beacon_interval(struct zd_chip *chip, u16 interval, u8 dtim_period, 926 int type); 927 zd_get_beacon_interval(struct zd_chip * chip,u32 * interval)928 static inline int zd_get_beacon_interval(struct zd_chip *chip, u32 *interval) 929 { 930 return zd_ioread32(chip, CR_BCN_INTERVAL, interval); 931 } 932 933 struct rx_status; 934 935 u8 zd_rx_rate(const void *rx_frame, const struct rx_status *status); 936 937 struct zd_mc_hash { 938 u32 low; 939 u32 high; 940 }; 941 zd_mc_clear(struct zd_mc_hash * hash)942 static inline void zd_mc_clear(struct zd_mc_hash *hash) 943 { 944 hash->low = 0; 945 /* The interfaces must always received broadcasts. 946 * The hash of the broadcast address ff:ff:ff:ff:ff:ff is 63. 947 */ 948 hash->high = 0x80000000; 949 } 950 zd_mc_add_all(struct zd_mc_hash * hash)951 static inline void zd_mc_add_all(struct zd_mc_hash *hash) 952 { 953 hash->low = hash->high = 0xffffffff; 954 } 955 zd_mc_add_addr(struct zd_mc_hash * hash,u8 * addr)956 static inline void zd_mc_add_addr(struct zd_mc_hash *hash, u8 *addr) 957 { 958 unsigned int i = addr[5] >> 2; 959 if (i < 32) { 960 hash->low |= 1 << i; 961 } else { 962 hash->high |= 1 << (i-32); 963 } 964 } 965 966 int zd_chip_set_multicast_hash(struct zd_chip *chip, 967 struct zd_mc_hash *hash); 968 969 u64 zd_chip_get_tsf(struct zd_chip *chip); 970 971 #endif /* _ZD_CHIP_H */ 972