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Searched refs:CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT (Results 1 – 13 of 13) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_7_2_sh_mask.h1428 #define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 macro
Dgfx_8_1_sh_mask.h2336 #define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 macro
Dgfx_8_0_sh_mask.h1812 #define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 macro
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h11182 #define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT … macro
Dgc_9_1_sh_mask.h12659 #define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT … macro
Dgc_9_4_3_sh_mask.h14199 #define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT … macro
Dgc_9_4_2_sh_mask.h2490 #define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT … macro
Dgc_11_5_0_sh_mask.h12328 #define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT … macro
Dgc_11_0_0_sh_mask.h15523 #define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT … macro
Dgc_12_0_0_sh_mask.h11938 #define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT … macro
Dgc_11_0_3_sh_mask.h17678 #define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT … macro
Dgc_10_1_0_sh_mask.h18137 #define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT … macro
Dgc_10_3_0_sh_mask.h16412 #define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT … macro