| /linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
| D | gfx_v11_0.c | 2508 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v11_0_config_pfp_cache_rs64()
2511 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v11_0_config_pfp_cache_rs64()
2517 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v11_0_config_pfp_cache_rs64()
2520 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v11_0_config_pfp_cache_rs64()
2631 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v11_0_config_me_cache_rs64()
2634 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v11_0_config_me_cache_rs64()
2640 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v11_0_config_me_cache_rs64()
2643 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v11_0_config_me_cache_rs64()
2791 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1); in gfx_v11_0_config_gfx_rs64()
2792 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1); in gfx_v11_0_config_gfx_rs64()
[all …]
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| D | gfx_v12_0.c | 1995 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1); in gfx_v12_0_config_gfx_rs64()
1996 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1); in gfx_v12_0_config_gfx_rs64()
2000 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0); in gfx_v12_0_config_gfx_rs64()
2001 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0); in gfx_v12_0_config_gfx_rs64()
2017 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1); in gfx_v12_0_config_gfx_rs64()
2018 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1); in gfx_v12_0_config_gfx_rs64()
2022 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0); in gfx_v12_0_config_gfx_rs64()
2023 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0); in gfx_v12_0_config_gfx_rs64()
2075 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v12_0_set_pfp_ucode_start_addr()
2078 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v12_0_set_pfp_ucode_start_addr()
[all …]
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| D | gfx_v8_0.c | 4095 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0); in gfx_v8_0_cp_gfx_enable()
4096 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0); in gfx_v8_0_cp_gfx_enable()
4097 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0); in gfx_v8_0_cp_gfx_enable()
4099 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1); in gfx_v8_0_cp_gfx_enable()
4100 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1); in gfx_v8_0_cp_gfx_enable()
4101 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1); in gfx_v8_0_cp_gfx_enable()
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| D | sid.h | 1025 #define CP_ME_CNTL 0x21B6 macro
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| D | gfx_v9_0.c | 3187 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); in gfx_v9_0_cp_gfx_enable()
3188 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); in gfx_v9_0_cp_gfx_enable()
3189 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); in gfx_v9_0_cp_gfx_enable()
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| D | gfx_v10_0.c | 5923 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); in gfx_v10_0_cp_gfx_enable()
5924 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); in gfx_v10_0_cp_gfx_enable()
5925 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); in gfx_v10_0_cp_gfx_enable()
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| /linux-6.12.1/drivers/gpu/drm/radeon/ |
| D | ni.c | 1438 WREG32(CP_ME_CNTL, 0); in cayman_cp_enable()
1442 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); in cayman_cp_enable()
1820 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); in cayman_gpu_soft_reset()
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| D | rv770d.h | 335 #define CP_ME_CNTL 0x86D8 macro
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| D | nid.h | 318 #define CP_ME_CNTL 0x86D8 macro
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| D | sid.h | 1027 #define CP_ME_CNTL 0x86D8 macro
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| D | cikd.h | 1108 #define CP_ME_CNTL 0x86D8 macro
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| D | si.c | 3443 WREG32(CP_ME_CNTL, 0); in si_cp_enable()
3447 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT)); in si_cp_enable()
3860 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); in si_gpu_soft_reset()
4029 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); in si_gpu_pci_config_reset()
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| D | evergreen.c | 3017 WREG32(CP_ME_CNTL, cp_me); in evergreen_cp_start()
3908 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); in evergreen_gpu_soft_reset()
4018 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); in evergreen_gpu_pci_config_reset()
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| D | rv770.c | 1084 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); in r700_cp_stop()
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| D | evergreend.h | 461 #define CP_ME_CNTL 0x86D8 macro
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| D | cik.c | 3866 WREG32(CP_ME_CNTL, 0); in cik_cp_gfx_enable()
3870 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT)); in cik_cp_gfx_enable()
4947 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); in cik_gpu_soft_reset()
5151 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); in cik_gpu_pci_config_reset()
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