Searched refs:CP_INT_CNTL (Results 1 – 13 of 13) sorted by relevance
| /linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
| D | gfx_v11_0.c | 4787 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 0); in gfx_v11_0_soft_reset()
4788 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 0); in gfx_v11_0_soft_reset()
4789 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 0); in gfx_v11_0_soft_reset()
4790 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 0); in gfx_v11_0_soft_reset()
4897 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); in gfx_v11_0_soft_reset()
4898 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); in gfx_v11_0_soft_reset()
4899 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); in gfx_v11_0_soft_reset()
4900 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); in gfx_v11_0_soft_reset()
5240 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); in gfx_v11_0_update_coarse_grain_clock_gating()
5241 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); in gfx_v11_0_update_coarse_grain_clock_gating()
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| D | gfx_v12_0.c | 3945 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); in gfx_v12_0_update_coarse_grain_clock_gating()
3946 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); in gfx_v12_0_update_coarse_grain_clock_gating()
3947 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); in gfx_v12_0_update_coarse_grain_clock_gating()
3948 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); in gfx_v12_0_update_coarse_grain_clock_gating()
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| D | gfx_v8_0.c | 6564 WREG32_FIELD(CP_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, enable_flag); in gfx_v8_0_set_cp_ecc_int_state()
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| /linux-6.12.1/drivers/gpu/drm/amd/pm/powerplay/inc/ |
| D | smu72_discrete.h | 499 uint32_t CP_INT_CNTL; member
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| D | smu74_discrete.h | 490 uint32_t CP_INT_CNTL; member
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| D | smu73_discrete.h | 481 uint32_t CP_INT_CNTL; member
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| D | smu75_discrete.h | 501 uint32_t CP_INT_CNTL; member
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| /linux-6.12.1/drivers/gpu/drm/radeon/ |
| D | nid.h | 494 #define CP_INT_CNTL 0xC124 macro
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| D | evergreend.h | 1246 #define CP_INT_CNTL 0xc124 macro
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| D | r600d.h | 714 #define CP_INT_CNTL 0xc124 macro
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| D | ni.c | 1370 WREG32(CP_INT_CNTL, cp_int_cntl); in cayman_cp_int_cntl_setup()
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| D | r600.c | 3622 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); in r600_disable_interrupt_state()
3873 WREG32(CP_INT_CNTL, cp_int_cntl); in r600_irq_set()
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| D | evergreen.c | 4470 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); in evergreen_disable_interrupt_state()
4565 WREG32(CP_INT_CNTL, cp_int_cntl); in evergreen_irq_set()
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