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Searched refs:CP_HQD_HQ_CONTROL0__CONTROL_MASK (Results 1 – 13 of 13) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_8_1_sh_mask.h4601 #define CP_HQD_HQ_CONTROL0__CONTROL_MASK 0xffffffff macro
Dgfx_8_0_sh_mask.h4079 #define CP_HQD_HQ_CONTROL0__CONTROL_MASK 0xffffffff macro
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h13049 #define CP_HQD_HQ_CONTROL0__CONTROL_MASK … macro
Dgc_9_1_sh_mask.h14349 #define CP_HQD_HQ_CONTROL0__CONTROL_MASK … macro
Dgc_9_4_3_sh_mask.h16581 #define CP_HQD_HQ_CONTROL0__CONTROL_MASK … macro
Dgc_9_2_1_sh_mask.h14214 #define CP_HQD_HQ_CONTROL0__CONTROL_MASK … macro
Dgc_9_4_2_sh_mask.h4147 #define CP_HQD_HQ_CONTROL0__CONTROL_MASK … macro
Dgc_11_5_0_sh_mask.h14282 #define CP_HQD_HQ_CONTROL0__CONTROL_MASK … macro
Dgc_11_0_0_sh_mask.h17588 #define CP_HQD_HQ_CONTROL0__CONTROL_MASK … macro
Dgc_12_0_0_sh_mask.h13479 #define CP_HQD_HQ_CONTROL0__CONTROL_MASK … macro
Dgc_11_0_3_sh_mask.h19833 #define CP_HQD_HQ_CONTROL0__CONTROL_MASK … macro
Dgc_10_1_0_sh_mask.h20468 #define CP_HQD_HQ_CONTROL0__CONTROL_MASK … macro
Dgc_10_3_0_sh_mask.h18621 #define CP_HQD_HQ_CONTROL0__CONTROL_MASK … macro