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Searched refs:CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK (Results 1 – 12 of 12) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Dnbio_v7_2.c242 CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK | in nbio_v7_2_update_medium_grain_clock_gating()
249 CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK | in nbio_v7_2_update_medium_grain_clock_gating()
Dnbio_v6_1.c172 CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK | in nbio_v6_1_update_medium_grain_clock_gating()
180 CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK | in nbio_v6_1_update_medium_grain_clock_gating()
Dnbio_v2_3.c240 CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK | in nbio_v2_3_update_medium_grain_clock_gating()
247 CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK | in nbio_v2_3_update_medium_grain_clock_gating()
Dnbio_v4_3.c250 CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK | in nbio_v4_3_update_medium_grain_clock_gating()
257 CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK | in nbio_v4_3_update_medium_grain_clock_gating()
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/pcie/
Dpcie_6_1_0_sh_mask.h3677 #define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK … macro
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/bif/
Dbif_5_0_sh_mask.h3667 #define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK 0x2 macro
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/nbio/
Dnbio_7_4_sh_mask.h44506 #define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK … macro
Dnbio_4_3_0_sh_mask.h33931 #define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK … macro
Dnbio_7_0_sh_mask.h75293 #define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK … macro
Dnbio_2_3_sh_mask.h56027 #define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK … macro
Dnbio_6_1_sh_mask.h39857 #define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK … macro
Dnbio_7_2_0_sh_mask.h101563 #define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK … macro