Searched refs:CPG_SD0CKCR (Results 1 – 7 of 7) sorted by relevance
| /linux-6.12.1/drivers/clk/renesas/ |
| D | clk-sh73a0.c | 25 #define CPG_SD0CKCR 0x74 macro
192 writel(0x108, base + CPG_SD0CKCR); in sh73a0_cpg_clocks_init()
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| D | r8a77970-cpg-mssr.c | 24 #define CPG_SD0CKCR 0x0074 macro
249 base + CPG_SD0CKCR, in r8a77970_cpg_clk_register()
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| D | r8a779f0-cpg-mssr.c | 118 DEF_GEN4_SDH("sd0h", R8A779F0_CLK_SD0H, CLK_SDSRC, CPG_SD0CKCR),
119 DEF_GEN4_SD("sd0", R8A779F0_CLK_SD0, R8A779F0_CLK_SD0H, CPG_SD0CKCR),
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| D | r8a779a0-cpg-mssr.c | 124 DEF_GEN4_SDH("sd0h", R8A779A0_CLK_SD0H, CLK_SDSRC, CPG_SD0CKCR),
125 DEF_GEN4_SD("sd0", R8A779A0_CLK_SD0, R8A779A0_CLK_SD0H, CPG_SD0CKCR),
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| D | r8a779g0-cpg-mssr.c | 154 DEF_GEN4_SDH("sd0h", R8A779G0_CLK_SD0H, CLK_SDSRC, CPG_SD0CKCR),
155 DEF_GEN4_SD("sd0", R8A779G0_CLK_SD0, R8A779G0_CLK_SD0H, CPG_SD0CKCR),
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| D | r8a779h0-cpg-mssr.c | 165 DEF_GEN4_SDH("sd0h", R8A779H0_CLK_SD0H, CLK_SDSRC, CPG_SD0CKCR),
166 DEF_GEN4_SD("sd0", R8A779H0_CLK_SD0, R8A779H0_CLK_SD0H, CPG_SD0CKCR),
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| D | rcar-gen4-cpg.h | 73 #define CPG_SD0CKCR 0x870 /* SD-IF0 Clock Frequency Control Register */ macro
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