Searched refs:CNVC_SURFACE_PIXEL_FORMAT (Results 1 – 13 of 13) sorted by relevance
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_ipp.h | 36 SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \
80 IPP_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_SURFACE_PIXEL_FORMAT, mask_sh), \
147 type CNVC_SURFACE_PIXEL_FORMAT; \
185 uint32_t CNVC_SURFACE_PIXEL_FORMAT; member
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dpp/dcn401/ |
| D | dcn401_dpp_cm.c | 96 REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0, in dpp401_full_bypass()
97 CNVC_SURFACE_PIXEL_FORMAT, 0x8); in dpp401_full_bypass()
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| D | dcn401_dpp.c | 190 REG_SET_2(CNVC_SURFACE_PIXEL_FORMAT, 0, in dpp401_dpp_setup()
191 CNVC_SURFACE_PIXEL_FORMAT, pixel_format, in dpp401_dpp_setup()
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| D | dcn401_dpp.h | 145 TF_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_SURFACE_PIXEL_FORMAT, mask_sh), \
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dpp/dcn201/ |
| D | dcn201_dpp.c | 173 REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0, in dpp201_cnv_setup()
174 CNVC_SURFACE_PIXEL_FORMAT, pixel_format); in dpp201_cnv_setup()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dpp/dcn20/ |
| D | dcn20_dpp.c | 227 REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0, in dpp2_cnv_setup()
228 CNVC_SURFACE_PIXEL_FORMAT, pixel_format); in dpp2_cnv_setup()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dpp/dcn10/ |
| D | dcn10_dpp.c | 380 REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0, in dpp1_cnv_setup()
381 CNVC_SURFACE_PIXEL_FORMAT, pixel_format); in dpp1_cnv_setup()
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| D | dcn10_dpp_cm.c | 776 REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0, in dpp1_full_bypass()
777 CNVC_SURFACE_PIXEL_FORMAT, 0x8); in dpp1_full_bypass()
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| D | dcn10_dpp.h | 121 SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \
328 TF_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_SURFACE_PIXEL_FORMAT, mask_sh), \
1074 type CNVC_SURFACE_PIXEL_FORMAT; \
1344 uint32_t CNVC_SURFACE_PIXEL_FORMAT; \
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dpp/dcn30/ |
| D | dcn30_dpp.h | 138 SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \
301 TF_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_SURFACE_PIXEL_FORMAT, mask_sh), \
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| D | dcn30_dpp.c | 344 REG_SET_2(CNVC_SURFACE_PIXEL_FORMAT, 0, in dpp3_cnv_setup()
345 CNVC_SURFACE_PIXEL_FORMAT, pixel_format, in dpp3_cnv_setup()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| D | dcn401_resource.h | 313 SRI_ARR(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| D | dcn32_resource.h | 511 SRI_ARR(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \
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