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Searched refs:CLK_VPP1_SVPP3_VDO0_DL_RELAY (Results 1 – 4 of 4) sorted by relevance

/linux-6.12.1/drivers/clk/mediatek/
Dclk-mt8188-vpp1.c75 GATE_VPP1_1(CLK_VPP1_SVPP3_VDO0_DL_RELAY, "vpp1_svpp3_vdo0_dl_relay", "top_vpp", 9),
Dclk-mt8195-vpp1.c72 GATE_VPP1_1(CLK_VPP1_SVPP3_VDO0_DL_RELAY, "vpp1_svpp3_vdo0_dl_relay", "top_vpp", 6),
/linux-6.12.1/include/dt-bindings/clock/
Dmediatek,mt8188-clk.h480 #define CLK_VPP1_SVPP3_VDO0_DL_RELAY 40 macro
Dmt8195-clk.h582 #define CLK_VPP1_SVPP3_VDO0_DL_RELAY 38 macro