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Searched refs:CLK_VPP1_SVPP2_MDP_RSZ (Results 1 – 5 of 5) sorted by relevance

/linux-6.12.1/drivers/clk/mediatek/
Dclk-mt8188-vpp1.c54 GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_RSZ, "vpp1_svpp2_mdp_rsz", "top_vpp", 20),
Dclk-mt8195-vpp1.c70 GATE_VPP1_1(CLK_VPP1_SVPP2_MDP_RSZ, "vpp1_svpp2_mdp_rsz", "top_vpp", 4),
/linux-6.12.1/include/dt-bindings/clock/
Dmediatek,mt8188-clk.h460 #define CLK_VPP1_SVPP2_MDP_RSZ 20 macro
Dmt8195-clk.h580 #define CLK_VPP1_SVPP2_MDP_RSZ 36 macro
/linux-6.12.1/arch/arm64/boot/dts/mediatek/
Dmt8195.dtsi2429 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RSZ>;