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Searched refs:CLK_VPP0_WARP1_ASYNC_TX (Results 1 – 4 of 4) sorted by relevance

/linux-6.12.1/drivers/clk/mediatek/
Dclk-mt8195-vpp0.c47 GATE_VPP0_0(CLK_VPP0_WARP1_ASYNC_TX, "vpp0_warp1_async_tx", "top_vpp", 11),
Dclk-mt8188-vpp0.c48 GATE_VPP0_0(CLK_VPP0_WARP1_ASYNC_TX, "vpp0_warp1_async_tx", "top_vpp", 11),
/linux-6.12.1/include/dt-bindings/clock/
Dmediatek,mt8188-clk.h364 #define CLK_VPP0_WARP1_ASYNC_TX 5 macro
Dmt8195-clk.h438 #define CLK_VPP0_WARP1_ASYNC_TX 5 macro