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Searched refs:CLK_VPP0_VPP12VPP0_ASYNC (Results 1 – 4 of 4) sorted by relevance

/linux-6.12.1/drivers/clk/mediatek/
Dclk-mt8195-vpp0.c50 GATE_VPP0_0(CLK_VPP0_VPP12VPP0_ASYNC, "vpp0_vpp12vpp0_async", "top_vpp", 15),
Dclk-mt8188-vpp0.c51 GATE_VPP0_0(CLK_VPP0_VPP12VPP0_ASYNC, "vpp0_vpp12vpp0_async", "top_vpp", 15),
/linux-6.12.1/include/dt-bindings/clock/
Dmediatek,mt8188-clk.h367 #define CLK_VPP0_VPP12VPP0_ASYNC 8 macro
Dmt8195-clk.h441 #define CLK_VPP0_VPP12VPP0_ASYNC 8 macro