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Searched refs:CLK_VPP02VPP1_RELAY (Results 1 – 2 of 2) sorted by relevance

/linux-6.12.1/drivers/clk/mediatek/
Dclk-mt8188-vpp0.c50 GATE_VPP0_0(CLK_VPP02VPP1_RELAY, "vpp02vpp1_relay", "top_vpp", 14),
/linux-6.12.1/include/dt-bindings/clock/
Dmediatek,mt8188-clk.h366 #define CLK_VPP02VPP1_RELAY 7 macro