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Searched refs:CLK_UART0_INTERNAL_DIV (Results 1 – 3 of 3) sorted by relevance

/linux-6.12.1/include/dt-bindings/clock/
Dpistachio-clk.h66 #define CLK_UART0_INTERNAL_DIV 76 macro
/linux-6.12.1/drivers/clk/pistachio/
Dclk-pistachio.c74 DIV_F(CLK_UART0_INTERNAL_DIV, "uart0_internal_div", "sys_pll_mux",
/linux-6.12.1/arch/mips/boot/dts/img/
Dpistachio.dtsi259 assigned-clocks = <&clk_core CLK_UART0_INTERNAL_DIV>,