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Searched refs:CLK_UART0_DIV (Results 1 – 5 of 5) sorted by relevance

/linux-6.12.1/include/dt-bindings/clock/
Dpistachio-clk.h67 #define CLK_UART0_DIV 77 macro
Drk3568-cru.h22 #define CLK_UART0_DIV 9 macro
/linux-6.12.1/drivers/clk/pistachio/
Dclk-pistachio.c76 DIV_F(CLK_UART0_DIV, "uart0_div", "uart0_internal_div", 0x238, 10,
/linux-6.12.1/arch/mips/boot/dts/img/
Dpistachio.dtsi260 <&clk_core CLK_UART0_DIV>;
/linux-6.12.1/drivers/clk/rockchip/
Dclk-rk3568.c1500 COMPOSITE(CLK_UART0_DIV, "sclk_uart0_div", ppll_usb480m_cpll_gpll_p, 0,