| /linux-6.12.1/include/dt-bindings/clock/ |
| D | exynos5410.h | 36 #define CLK_UART0 257 macro
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| D | actions,s500-cmu.h | 58 #define CLK_UART0 38 macro
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| D | actions,s700-cmu.h | 58 #define CLK_UART0 36 macro
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| D | actions,s900-cmu.h | 85 #define CLK_UART0 67 macro
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| D | pistachio-clk.h | 39 #define CLK_UART0 48 macro
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| D | sophgo,cv1800.h | 88 #define CLK_UART0 77 macro
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| D | exynos5250.h | 93 #define CLK_UART0 289 macro
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| D | s5pv210.h | 161 #define CLK_UART0 143 macro
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| D | exynos4.h | 150 #define CLK_UART0 312 macro
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| D | exynos5420.h | 66 #define CLK_UART0 257 macro
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| D | exynos3250.h | 222 #define CLK_UART0 216 macro
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| D | sprd,ums512-clk.h | 139 #define CLK_UART0 11 macro
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| D | sprd,sc9860-clk.h | 85 #define CLK_UART0 2 macro
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| D | rockchip,rk3588-cru.h | 681 #define CLK_UART0 666 macro
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| /linux-6.12.1/drivers/clk/samsung/ |
| D | clk-exynos5410.c | 200 GATE(CLK_UART0, "uart0", "aclk66", GATE_IP_PERIC, 0, 0, 0),
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| D | clk-s5pv210.c | 576 GATE(CLK_UART0, "uart0", "dout_pclkp", CLK_GATE_IP3, 17, 0, 0),
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| /linux-6.12.1/drivers/clk/pistachio/ |
| D | clk-pistachio.c | 35 GATE(CLK_UART0, "uart0", "uart0_div", 0x104, 16),
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| /linux-6.12.1/arch/arm/boot/dts/samsung/ |
| D | s5pv210.dtsi | 321 clocks = <&clocks CLK_UART0>, <&clocks CLK_UART0>,
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| D | exynos5410.dtsi | 340 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
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| /linux-6.12.1/arch/arm64/boot/dts/actions/ |
| D | s700.dtsi | 119 clocks = <&cmu CLK_UART0>;
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| D | s900.dtsi | 125 clocks = <&cmu CLK_UART0>;
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| /linux-6.12.1/arch/arm64/boot/dts/sprd/ |
| D | whale2.dtsi | 78 <&ap_clk CLK_UART0>,
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| /linux-6.12.1/arch/riscv/boot/dts/sophgo/ |
| D | cv18xx.dtsi | 195 clocks = <&clk CLK_UART0>, <&clk CLK_APB_UART0>;
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| /linux-6.12.1/arch/arm/boot/dts/actions/ |
| D | owl-s500.dtsi | 136 clocks = <&cmu CLK_UART0>;
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| /linux-6.12.1/drivers/clk/actions/ |
| D | owl-s500.c | 489 [CLK_UART0] = &uart0_clk.common.hw,
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