| /linux-6.12.1/arch/arm/boot/dts/mediatek/ |
| D | mt7629.dtsi | 101 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
324 <&topckgen CLK_TOP_UNIVPLL1_D2>;
392 <&topckgen CLK_TOP_UNIVPLL1_D2>;
468 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>,
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| /linux-6.12.1/include/dt-bindings/clock/ |
| D | mt8135-clk.h | 43 #define CLK_TOP_UNIVPLL1_D2 32 macro
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| D | mt7629-clk.h | 50 #define CLK_TOP_UNIVPLL1_D2 40 macro
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| D | mt7622-clk.h | 44 #define CLK_TOP_UNIVPLL1_D2 32 macro
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| D | mediatek,mt6795-clk.h | 71 #define CLK_TOP_UNIVPLL1_D2 60 macro
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| D | mt6797-clk.h | 68 #define CLK_TOP_UNIVPLL1_D2 58 macro
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| D | mt8173-clk.h | 73 #define CLK_TOP_UNIVPLL1_D2 63 macro
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| D | mt6765-clk.h | 58 #define CLK_TOP_UNIVPLL1_D2 23 macro
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| D | mediatek,mt8365-clk.h | 33 #define CLK_TOP_UNIVPLL1_D2 23 macro
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| D | mt2712-clk.h | 57 #define CLK_TOP_UNIVPLL1_D2 26 macro
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| D | mt2701-clk.h | 36 #define CLK_TOP_UNIVPLL1_D2 26 macro
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| /linux-6.12.1/drivers/clk/mediatek/ |
| D | clk-mt6795-topckgen.c | 427 FACTOR_FLAGS(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univ_624m", 1, 2, 0),
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| D | clk-mt8173-topckgen.c | 506 FACTOR_FLAGS(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univ_624m", 1, 2, 0),
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| D | clk-mt7622.c | 286 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4),
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| D | clk-mt8135.c | 63 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_624m", 1, 2),
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| D | clk-mt7629.c | 393 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4),
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| D | clk-mt6797.c | 48 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2),
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| D | clk-mt8365.c | 52 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4),
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| D | clk-mt2712.c | 65 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2),
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| D | clk-mt2701.c | 83 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2),
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| D | clk-mt6765.c | 108 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2),
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| /linux-6.12.1/arch/arm64/boot/dts/mediatek/ |
| D | mt2712e.dtsi | 322 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
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