| /linux-6.12.1/include/dt-bindings/clock/ |
| D | mt8135-clk.h | 41 #define CLK_TOP_SYSPLL_D5 30 macro
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| D | mt7629-clk.h | 42 #define CLK_TOP_SYSPLL_D5 32 macro
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| D | mt7622-clk.h | 36 #define CLK_TOP_SYSPLL_D5 24 macro
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| D | mediatek,mt6795-clk.h | 59 #define CLK_TOP_SYSPLL_D5 48 macro
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| D | mt6797-clk.h | 56 #define CLK_TOP_SYSPLL_D5 46 macro
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| D | mt8173-clk.h | 61 #define CLK_TOP_SYSPLL_D5 51 macro
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| D | mt6765-clk.h | 45 #define CLK_TOP_SYSPLL_D5 10 macro
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| D | mediatek,mt8365-clk.h | 25 #define CLK_TOP_SYSPLL_D5 15 macro
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| D | mt2712-clk.h | 44 #define CLK_TOP_SYSPLL_D5 13 macro
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| D | mt8183-clk.h | 81 #define CLK_TOP_SYSPLL_D5 45 macro
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| D | mt2701-clk.h | 14 #define CLK_TOP_SYSPLL_D5 4 macro
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| /linux-6.12.1/drivers/clk/mediatek/ |
| D | clk-mt6795-topckgen.c | 413 FACTOR_FLAGS(CLK_TOP_SYSPLL_D5, "syspll_d5", "main_h218p4m", 1, 1, 0),
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| D | clk-mt8173-topckgen.c | 492 FACTOR_FLAGS(CLK_TOP_SYSPLL_D5, "syspll_d5", "main_h218p4m", 1, 1, 0),
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| D | clk-mt7622.c | 278 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
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| D | clk-mt8135.c | 59 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll_322p4m", 1, 1),
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| D | clk-mt7629.c | 385 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
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| D | clk-mt6797.c | 36 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
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| D | clk-mt8183.c | 45 FACTOR_FLAGS(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5, 0),
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| D | clk-mt8365.c | 44 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
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| D | clk-mt2712.c | 52 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "syspll_ck", 1, 5),
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| D | clk-mt2701.c | 60 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
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| D | clk-mt6765.c | 93 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
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