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Searched refs:CLK_TOP_SYSPLL4_D2 (Results 1 – 18 of 18) sorted by relevance

/linux-6.12.1/include/dt-bindings/clock/
Dmt7629-clk.h46 #define CLK_TOP_SYSPLL4_D2 36 macro
Dmt7622-clk.h39 #define CLK_TOP_SYSPLL4_D2 27 macro
Dmediatek,mt6795-clk.h63 #define CLK_TOP_SYSPLL4_D2 52 macro
Dmt6797-clk.h60 #define CLK_TOP_SYSPLL4_D2 50 macro
Dmt8173-clk.h65 #define CLK_TOP_SYSPLL4_D2 55 macro
Dmt6765-clk.h49 #define CLK_TOP_SYSPLL4_D2 14 macro
Dmediatek,mt8365-clk.h29 #define CLK_TOP_SYSPLL4_D2 19 macro
Dmt2712-clk.h48 #define CLK_TOP_SYSPLL4_D2 17 macro
Dmt2701-clk.h25 #define CLK_TOP_SYSPLL4_D2 15 macro
/linux-6.12.1/drivers/clk/mediatek/
Dclk-mt6795-topckgen.c417 FACTOR_FLAGS(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "main_h156m", 1, 2, 0),
Dclk-mt8173-topckgen.c496 FACTOR_FLAGS(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "main_h156m", 1, 2, 0),
Dclk-mt7622.c281 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 14),
Dclk-mt7629.c389 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 14),
Dclk-mt6797.c40 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2),
Dclk-mt8365.c48 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 14),
Dclk-mt2712.c56 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2),
Dclk-mt2701.c71 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2),
Dclk-mt6765.c97 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2),