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Searched refs:CLK_TOP_SYSPLL1_D8 (Results 1 – 18 of 18) sorted by relevance

/linux-6.12.1/include/dt-bindings/clock/
Dmt7629-clk.h37 #define CLK_TOP_SYSPLL1_D8 27 macro
Dmt7622-clk.h33 #define CLK_TOP_SYSPLL1_D8 21 macro
Dmediatek,mt6795-clk.h54 #define CLK_TOP_SYSPLL1_D8 43 macro
Dmt6797-clk.h49 #define CLK_TOP_SYSPLL1_D8 39 macro
Dmt8173-clk.h56 #define CLK_TOP_SYSPLL1_D8 46 macro
Dmt6765-clk.h39 #define CLK_TOP_SYSPLL1_D8 4 macro
Dmediatek,mt8365-clk.h19 #define CLK_TOP_SYSPLL1_D8 9 macro
Dmt2712-clk.h39 #define CLK_TOP_SYSPLL1_D8 8 macro
Dmt2701-clk.h18 #define CLK_TOP_SYSPLL1_D8 8 macro
/linux-6.12.1/drivers/clk/mediatek/
Dclk-mt6795-topckgen.c408 FACTOR_FLAGS(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "main_h546m", 1, 8, 0),
Dclk-mt8173-topckgen.c487 FACTOR_FLAGS(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "main_h546m", 1, 8, 0),
Dclk-mt7622.c275 FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "mainpll", 1, 16),
Dclk-mt7629.c380 FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "mainpll", 1, 16),
Dclk-mt6797.c29 FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, 8),
Dclk-mt8365.c38 FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "mainpll", 1, 16),
Dclk-mt2712.c47 FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, 8),
Dclk-mt2701.c64 FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, 8),
Dclk-mt6765.c87 FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, 8),