| /linux-6.12.1/include/dt-bindings/clock/ |
| D | mt7986-clk.h | 54 #define CLK_TOP_PWM_SEL 31 macro
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| D | mt7629-clk.h | 87 #define CLK_TOP_PWM_SEL 77 macro
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| D | mediatek,mt7981-clk.h | 94 #define CLK_TOP_PWM_SEL 81 macro
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| D | mt8516-clk.h | 188 #define CLK_TOP_PWM_SEL 156 macro
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| D | mt7622-clk.h | 72 #define CLK_TOP_PWM_SEL 60 macro
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| D | mediatek,mt7988-clk.h | 74 #define CLK_TOP_PWM_SEL 46 macro
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| D | mediatek,mt6795-clk.h | 94 #define CLK_TOP_PWM_SEL 83 macro
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| D | mt8173-clk.h | 96 #define CLK_TOP_PWM_SEL 86 macro
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| D | mt6765-clk.h | 156 #define CLK_TOP_PWM_SEL 121 macro
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| D | mediatek,mt8365-clk.h | 99 #define CLK_TOP_PWM_SEL 89 macro
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| D | mt2712-clk.h | 133 #define CLK_TOP_PWM_SEL 102 macro
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| D | mt2701-clk.h | 94 #define CLK_TOP_PWM_SEL 83 macro
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| D | mt8192-clk.h | 66 #define CLK_TOP_PWM_SEL 54 macro
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| /linux-6.12.1/drivers/clk/mediatek/ |
| D | clk-mt7986-topckgen.c | 186 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010,
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| D | clk-mt7981-topckgen.c | 303 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
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| D | clk-mt7988-topckgen.c | 143 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x040, 0x044, 0x048, 0, 3, 7,
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| D | clk-mt6795-topckgen.c | 460 TOP_MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x50, 0, 2, 7, 0),
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| D | clk-mt8173-topckgen.c | 539 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0050, 0, 2, 7),
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| D | clk-mt7622.c | 396 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
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| D | clk-mt8516.c | 421 MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
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| D | clk-mt7629.c | 471 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
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| D | clk-mt8167.c | 610 MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
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| D | clk-mt8365.c | 490 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0b0,
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| D | clk-mt2712.c | 650 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x050, 0, 2, 7),
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| /linux-6.12.1/arch/arm/boot/dts/mediatek/ |
| D | mt7629.dtsi | 247 clocks = <&topckgen CLK_TOP_PWM_SEL>,
251 assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>;
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