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Searched refs:CLK_TOP_MUX_AUD_2 (Results 1 – 10 of 10) sorted by relevance

/linux-6.12.1/sound/soc/mediatek/mt8183/
Dmt8183-afe-clk.c32 CLK_TOP_MUX_AUD_2, enumerator
71 [CLK_TOP_MUX_AUD_2] = "top_mux_aud_2",
311 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_2]); in apll2_mux_setting()
314 __func__, aud_clks[CLK_TOP_MUX_AUD_2], ret); in apll2_mux_setting()
317 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2], in apll2_mux_setting()
321 __func__, aud_clks[CLK_TOP_MUX_AUD_2], in apll2_mux_setting()
352 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2], in apll2_mux_setting()
356 __func__, aud_clks[CLK_TOP_MUX_AUD_2], in apll2_mux_setting()
360 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_2]); in apll2_mux_setting()
371 clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2], in apll2_mux_setting()
[all …]
/linux-6.12.1/sound/soc/mediatek/mt8192/
Dmt8192-afe-clk.c32 [CLK_TOP_MUX_AUD_2] = "top_mux_aud_2",
148 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_2]); in apll2_mux_setting()
151 __func__, aud_clks[CLK_TOP_MUX_AUD_2], ret); in apll2_mux_setting()
154 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2], in apll2_mux_setting()
158 __func__, aud_clks[CLK_TOP_MUX_AUD_2], in apll2_mux_setting()
189 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2], in apll2_mux_setting()
193 __func__, aud_clks[CLK_TOP_MUX_AUD_2], in apll2_mux_setting()
197 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_2]); in apll2_mux_setting()
567 CLK_TOP_MUX_AUD_1 : CLK_TOP_MUX_AUD_2; in mt8192_mck_enable()
Dmt8192-afe-clk.h189 CLK_TOP_MUX_AUD_2, enumerator
/linux-6.12.1/sound/soc/mediatek/mt8186/
Dmt8186-afe-clk.c53 [CLK_TOP_MUX_AUD_2] = "top_mux_aud_2",
158 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_2]); in apll2_mux_setting()
161 __func__, aud_clks[CLK_TOP_MUX_AUD_2], ret); in apll2_mux_setting()
164 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2], in apll2_mux_setting()
168 __func__, aud_clks[CLK_TOP_MUX_AUD_2], in apll2_mux_setting()
199 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2], in apll2_mux_setting()
203 __func__, aud_clks[CLK_TOP_MUX_AUD_2], in apll2_mux_setting()
207 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_2]); in apll2_mux_setting()
545 CLK_TOP_MUX_AUD_1 : CLK_TOP_MUX_AUD_2; in mt8186_mck_enable()
Dmt8186-afe-clk.h60 CLK_TOP_MUX_AUD_2, enumerator
/linux-6.12.1/include/dt-bindings/clock/
Dmt6797-clk.h38 #define CLK_TOP_MUX_AUD_2 28 macro
Dmt8183-clk.h56 #define CLK_TOP_MUX_AUD_2 20 macro
/linux-6.12.1/drivers/clk/mediatek/
Dclk-mt6797.c366 MUX_GATE(CLK_TOP_MUX_AUD_2, "aud_2_sel", aud_2_parents,
Dclk-mt8183.c554 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_2, "aud_2_sel",
/linux-6.12.1/arch/arm64/boot/dts/mediatek/
Dmt8183.dtsi1480 <&topckgen CLK_TOP_MUX_AUD_2>,