Searched refs:CLK_TOP_MSDC50_0 (Results 1 – 13 of 13) sorted by relevance
| /linux-6.12.1/include/dt-bindings/clock/ |
| D | mt6765-clk.h | 95 #define CLK_TOP_MSDC50_0 60 macro
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| D | mt6779-clk.h | 19 #define CLK_TOP_MSDC50_0 9 macro
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| D | mt8186-clk.h | 32 #define CLK_TOP_MSDC50_0 13 macro
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| D | mediatek,mt8188-clk.h | 38 #define CLK_TOP_MSDC50_0 27 macro
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| D | mt8195-clk.h | 42 #define CLK_TOP_MSDC50_0 30 macro
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| /linux-6.12.1/drivers/clk/mediatek/ |
| D | clk-mt8186-topckgen.c | 536 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0, "top_msdc50_0",
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| D | clk-mt8188-topckgen.c | 1019 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0, "top_msdc50_0",
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| D | clk-mt8195-topckgen.c | 946 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0, "top_msdc50_0",
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| D | clk-mt6779.c | 691 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0, "msdc50_0_sel",
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| D | clk-mt6765.c | 143 FACTOR(CLK_TOP_MSDC50_0, "msdc50_0_ck", "msdc50_0_sel", 1, 1),
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| /linux-6.12.1/arch/arm64/boot/dts/mediatek/ |
| D | mt8186.dtsi | 1597 clocks = <&topckgen CLK_TOP_MSDC50_0>,
1603 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0>;
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| D | mt8188.dtsi | 1490 clocks = <&topckgen CLK_TOP_MSDC50_0>,
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| D | mt8195.dtsi | 1392 clocks = <&topckgen CLK_TOP_MSDC50_0>,
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