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Searched refs:CLK_TOP_MM_SEL (Results 1 – 19 of 19) sorted by relevance

/linux-6.12.1/arch/arm64/boot/dts/mediatek/
Dmt6795.dtsi304 clocks = <&topckgen CLK_TOP_MM_SEL>;
310 clocks = <&topckgen CLK_TOP_MM_SEL>,
317 clocks = <&topckgen CLK_TOP_MM_SEL>;
324 clocks = <&topckgen CLK_TOP_MM_SEL>;
332 clocks = <&topckgen CLK_TOP_MM_SEL>,
723 assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
Dmt8173.dtsi459 clocks = <&topckgen CLK_TOP_MM_SEL>;
465 clocks = <&topckgen CLK_TOP_MM_SEL>,
472 clocks = <&topckgen CLK_TOP_MM_SEL>;
478 clocks = <&topckgen CLK_TOP_MM_SEL>;
485 clocks = <&topckgen CLK_TOP_MM_SEL>,
1000 assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
Dmt8365.dtsi318 clocks = <&topckgen CLK_TOP_MM_SEL>,
Dmt2712e.dtsi285 clocks = <&topckgen CLK_TOP_MM_SEL>,
/linux-6.12.1/include/dt-bindings/clock/
Dmediatek,mt6795-clk.h93 #define CLK_TOP_MM_SEL 82 macro
Dmt8173-clk.h95 #define CLK_TOP_MM_SEL 85 macro
Dmt6765-clk.h133 #define CLK_TOP_MM_SEL 98 macro
Dmediatek,mt8365-clk.h73 #define CLK_TOP_MM_SEL 63 macro
Dmt2712-clk.h132 #define CLK_TOP_MM_SEL 101 macro
Dmt2701-clk.h87 #define CLK_TOP_MM_SEL 76 macro
/linux-6.12.1/Documentation/devicetree/bindings/soc/mediatek/
Dscpsys.txt67 <&topckgen CLK_TOP_MM_SEL>;
/linux-6.12.1/drivers/clk/mediatek/
Dclk-mt6795-topckgen.c458 TOP_MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x40, 24, 3, 31, 0),
Dclk-mt8173-topckgen.c537 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x0040, 24, 4, 31),
Dclk-mt8365.c415 MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x040, 0x044,
Dclk-mt2712.c648 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x040, 24, 3, 31),
Dclk-mt2701.c493 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents,
Dclk-mt6765.c376 MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_parents, CLK_CFG_0,
/linux-6.12.1/arch/arm/boot/dts/mediatek/
Dmt2701.dtsi156 clocks = <&topckgen CLK_TOP_MM_SEL>,
Dmt7623.dtsi277 clocks = <&topckgen CLK_TOP_MM_SEL>,