Searched refs:CLK_TOP_ETH_SYS_SEL (Results 1 – 2 of 2) sorted by relevance
105 #define CLK_TOP_ETH_SYS_SEL 77 macro
212 MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_SEL, "eth_sys_sel", pcie_mbist_250m_parents, 0x0b0,