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Searched refs:CLK_TOP_DISP_PWM_SEL (Results 1 – 7 of 7) sorted by relevance

/linux-6.12.1/include/dt-bindings/clock/
Dmt6765-clk.h150 #define CLK_TOP_DISP_PWM_SEL 115 macro
Dmediatek,mt8365-clk.h93 #define CLK_TOP_DISP_PWM_SEL 83 macro
Dmt8192-clk.h45 #define CLK_TOP_DISP_PWM_SEL 33 macro
/linux-6.12.1/drivers/clk/mediatek/
Dclk-mt8365.c471 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL, "disp_pwm_sel",
Dclk-mt8192.c626 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL, "disp_pwm_sel",
Dclk-mt6765.c431 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL, "disp_pwm_sel",
/linux-6.12.1/arch/arm64/boot/dts/mediatek/
Dmt8192.dtsi829 clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>,